Issued Patents All Time
Showing 25 most recent of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423058 | Systolic array with input reduction to multiple reduced inputs | Thomas A. Volpe, Ron Diamant, Joshua W. Bowman, Nishith Desai, Thomas Elmer | 2025-09-23 |
| 12380321 | Flexible array data loading | Ron Diamant | 2025-08-05 |
| 12271732 | Configuration of a deep vector engine using an opcode table, control table, and datapath table | Ron Diamant, Sundeep Amirineni | 2025-04-08 |
| 12260214 | Throughput increase for compute engine | Ron Diamant, Sundeep Amirineni, Sunil Kumar Bathula | 2025-03-25 |
| 12242853 | Configurable vector compute engine | Ron Diamant, Sundeep Amirineni | 2025-03-04 |
| 12182695 | Fine-grained sparsity computations in systolic array | Thiam Khean Hah, Randy Renfu Huang, Ron Diamant, Vignesh Vivekraja | 2024-12-31 |
| 12182691 | Increasing performance of computational array accelerators | Sundeep Amirineni, Akshay Balasubramanian, Joshua W. Bowman, Ron Diamant, Thomas Elmer | 2024-12-31 |
| 12141468 | Matrix transpose hardware acceleration | Kun Xu, Ron Diamant | 2024-11-12 |
| 12130885 | Emulating fine-grained sparsity in a systolic array | Thiam Khean Hah, Randy Renfu Huang, Ron Diamant, Vignesh Vivekraja | 2024-10-29 |
| 12099840 | Throughput increase for tensor operations | Xiaodan Tan, Ron Diamant | 2024-09-24 |
| 12045475 | Resizable scratchpad memory | Patricio Kaplan, Sundeep Amirineni, Laura Sharpless, Ron Diamant, Akshay Balasubramanian | 2024-07-23 |
| 12039330 | Programmable vector engine for efficient beam search | — | 2024-07-16 |
| 12008368 | Programmable compute engine having transpose operations | Xiaodan Tan, Sheng Xu, Ron Diamant | 2024-06-11 |
| 11941397 | Machine instructions for decoding acceleration including fuse input instructions to fuse multiple JPEG data blocks together to take advantage of a full SIMD width of a processor | Xiaodan Tan | 2024-03-26 |
| 11880682 | Systolic array with efficient input reduction and extended array performance | Thomas A. Volpe, Ron Diamant, Joshua W. Bowman, Nishith Desai, Thomas Elmer | 2024-01-23 |
| 11803736 | Fine-grained sparsity computations in systolic array | Thiam Khean Hah, Randy Renfu Huang, Ron Diamant, Vignesh Vivekraja | 2023-10-31 |
| 11625453 | Using shared data bus to support systolic array tiling | Ron Diamant | 2023-04-11 |
| 11500962 | Emulating fine-grained sparsity in a systolic array | Thiam Khean Hah, Randy Renfu Huang, Ron Diamant, Vignesh Vivekraja | 2022-11-15 |
| 11435941 | Matrix transpose hardware acceleration | Kun Xu, Ron Diamant | 2022-09-06 |
| 11314648 | Data processing | Michael Filippo, Jamshed Jalal, Kias Magnus Bruce, Alex James Waugh, Geoffray Matthieu Lacourba +2 more | 2022-04-26 |
| 11256623 | Cache content management | Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal, Klas Magnus Bruce, Michael Filippo +2 more | 2022-02-22 |
| 10783080 | Cache maintenance operations in a data processing system | Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal | 2020-09-22 |
| 10761987 | Apparatus and method for processing an ownership upgrade request for cached data that is issued in relation to a conditional store operation | Jamshed Jalal, Mark David Werkheiser, Michael Filippo, Klas Magnus Bruce | 2020-09-01 |
| 10713187 | Memory controller having data access hint message for specifying the given range of one or more memory addresses | Michael Filippo, Jamshed Jalal, Klas Magnus Bruce, David Joseph Hawkins, Phanindra Kumar Mannava +1 more | 2020-07-14 |
| 10698825 | Inter-chip communication in a multi-chip system | Gurunath Ramagiri, Ashok Kumar Tummala, Mark David Werkheiser, Jamshed Jalal, Premkishore Shivakumar | 2020-06-30 |