MF

Michael Filippo

NV NVIDIA: 38 patents #115 of 7,811Top 2%
AM AMD: 14 patents #820 of 9,279Top 9%
Overall (All Time): #50,762 of 4,157,543Top 2%
52
Patents All Time

Issued Patents All Time

Showing 25 most recent of 52 patents

Patent #TitleCo-InventorsDate
11663014 Speculatively executing instructions that follow a status updating instruction Abhishek Raja, Rakesh Shaji Lal, Glen Andrew Harris, Vasu Kudaravalli, Huzefa Sanjeliwala +1 more 2023-05-30
11409530 System, method and apparatus for executing instructions Curtis Glenn Dunham, Pavel Shamis, Jamshed Jalal 2022-08-09
11392378 Executing a set of load operations for a gather-load instruction and controlling handling of another instruction that depends on completion of the gather-load instruction Abhishek Raja, Huzefa Sanjeliwala, Kelvin D. Goveas 2022-07-19
11327791 Apparatus and method for operating an issue queue Michael Achenbach, Robert G. McDonald, Nicholas Andrew PFISTER, Kelvin D. Goveas, . ABHISHEK RAJA +1 more 2022-05-10
11314648 Data processing Jamshed Jalal, Kias Magnus Bruce, Alex James Waugh, Geoffray Matthieu Lacourba, Paul Gilbert Meyer +2 more 2022-04-26
11263138 Correlated addresses and prefetching Joseph Michael Pusdesris, Miles Robert Dooley 2022-03-01
11256623 Cache content management Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal, Klas Magnus Bruce, Paul Gilbert Meyer +2 more 2022-02-22
11237974 Operation cache compression Michael Brian SCHINZLER 2022-02-01
11200177 Cache retention data management Alex James Waugh, Dimitrios Kaseridis, Klas Magnus Bruce, Joseph Michael Pusdesris, Jamshed Jalal 2021-12-14
11003454 Apparatus and method for speculative execution of instructions Michael Brian SCHINZLER, Yasuo Ishii 2021-05-11
10983916 Cache storage Huzefa Sanjeliwala, Klas Magnus Bruce, Leigang Kou, Miles Robert Dooley, Matthew A. Rafacz 2021-04-20
10817298 Shortcut path for a branch target buffer Yasuo Ishii, Muhammad Umar Farooq 2020-10-27
10761987 Apparatus and method for processing an ownership upgrade request for cached data that is issued in relation to a conditional store operation Jamshed Jalal, Mark David Werkheiser, Klas Magnus Bruce, Paul Gilbert Meyer 2020-09-01
10754687 Scheduling in a data processing apparatus . ABHISHEK RAJA, Chris Abernathy 2020-08-25
10713187 Memory controller having data access hint message for specifying the given range of one or more memory addresses Jamshed Jalal, Klas Magnus Bruce, Paul Gilbert Meyer, David Joseph Hawkins, Phanindra Kumar Mannava +1 more 2020-07-14
10572259 Hints in a data processing apparatus Jesse Garrett Beu, Alejandro Rico Carro, Lee Evan Eisen 2020-02-25
10552338 Technique for efficient utilisation of an address translation cache Abhishek Raja 2020-02-04
10545877 Apparatus and method for accessing an address translation cache Abhishek Raja 2020-01-28
10503660 Technique for determining address translation data to be stored within an address translation cache Abhishek Raja 2019-12-10
10402349 Memory controller having data access hint message for specifying the given range of one or more memory addresses Jamshed Jalal, Klas Magnus Bruce, Paul Gilbert Meyer, David Joseph Hawkins, Phanindra Kumar Mannava +1 more 2019-09-03
10310862 Data processing Robert G. McDonald, Glen Andrew Harris 2019-06-04
10289417 Branch prediction suppression for blocks of instructions predicted to not include a branch instruction Matthew Paul Elwood, Umar Farooq, Adam George 2019-05-14
10268581 Cache hierarchy management Klas Magnus Bruce, Vasu Kudaravalli, Adam George, Muhammad Umar Farooq, Joseph Michael Pusdesris 2019-04-23
10229066 Queuing memory access requests Miles Robert Dooley, Matthew A. Rafacz, Huzefa Sanjeliwala 2019-03-12
10185663 Cache bypass Jamshed Jalal, Bruce James Mathewson, Phanindra Kumar Mannava 2019-01-22