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James K. Pickett — 52 Patents

AMD: 46 patents #162 of 9,280Top 2%

DEDelco Electronics: 4 patents #87 of 908Top 10%

Intel: 1 patents #18,326 of 30,777Top 60%

Austin, TX: #431 of 18,064 inventorsTop 3%

Texas: #1,624 of 125,132 inventorsTop 2%

Overall (All Time): #50,240 of 4,157,543Top 2%

52 Patents All Time

James K. Pickett has been granted 52 US patents while listed as an inventor at AMD. The first was granted in 1988 and the most recent in December 2018. James K. Pickett ranks #50,240 of 4,157,543 US inventors in our database (top 1.2%). Patent records list James K. Pickett in Austin, TX, US.

Patents per Year

Issued Patents All Time

Showing 1–25 of 52 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
10163508	Supporting multiple memory types in a memory slot	Woojong Han, Mohamed Arafa, Brian S. Morris, Mani N. Prakash, John K. Grooms +3 more	2018-12-25
7836259	Prefetch unit for use with a cache memory subsystem of a cache memory hierarchy	Michael Filippo, Roger D. Isaac	2010-11-16	$9,175,000
7415597	Processor with dependence mechanism to predict whether a load is dependent on older store	Michael Filippo	2008-08-19	$10,246,000
7363470	System and method to prevent in-flight instances of operations from disrupting operation replay within a data-speculative microprocessor	Michael Filippo, Benjamin T. Sander	2008-04-22	$9,226,000
7321964	Store-to-load forwarding buffer using indexed lookup	Michael Filippo	2008-01-22	$21,379,000
7266673	Speculation pointers to identify data-speculative operations in microprocessor	Michael Filippo, Benjamin T. Sander	2007-09-04	$16,316,000
7251710	Cache memory subsystem including a fixed latency R/W pipeline	Roger D. Isaac, Mitchell Alsup, Rama S. Gopal, Michael Filippo	2007-07-31	$9,995,000
7222226	System and method for modifying a load operation to include a register-to-register move operation in order to forward speculative load results to a dependent operation	Kevin M. Lepak, Benjamin T. Sander	2007-05-22	$14,345,000
7165167	Load store unit with replay mechanism	Michael Filippo, Benjamin T. Sander, Rama S. Gopal	2007-01-16	$16,173,000
7133969	System and method for handling exceptional instructions in a trace cache based processor	Mitchell Alsup, Gregory W. Smaus, Brian D. McMinn, Michael Filippo, Benjamin T. Sander	2006-11-07	$14,140,000
7089400	Data speculation based on stack-relative addressing patterns	Benjamin T. Sander, Kevin M. Lepak	2006-08-08	$20,246,000
7043626	Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming	Brian D. McMinn, Mitchell Alsup	2006-05-09	$10,311,000
7028166	System and method for linking speculative results of load operations to register values	—	2006-04-11	$9,016,000
7024537	Data speculation based on addressing patterns identifying dual-purpose register	Benjamin T. Sander, Kevin M. Lepak	2006-04-04	$14,413,000
6957319	Integrated circuit with multiple microcode ROMs	Brian D. McMinn	2005-10-18	$5,936,000
6957322	Efficient microcode entry access from sequentially addressed portion via non-sequentially addressed portion	—	2005-10-18	$5,936,000
6944744	Apparatus and method for independently schedulable functional units with issue lock mechanism in a processor	Ashraf Ahmed, Michael Filippo	2005-09-13	$9,865,000
6845442	System and method of using speculative operand sources in order to speculatively bypass load-store operations	Kevin M. Lepak, Benjamin T. Sander	2005-01-18	$6,792,000
6826704	Microprocessor employing a performance throttling mechanism for power management	—	2004-11-30	$7,368,000
6438664	Microcode patch device and method for patching microcode using match registers and patch routines	Kevin J. McGrath	2002-08-20	$3,107,000
6298424	Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation	W. Kurt Lewchuk, Brian D. McMinn	2001-10-02	$2,425,000
6202139	Pipelined data cache with multiple ports and processor with load/store unit selecting only load or store operations for concurrent processing	David B. Witt	2001-03-13	$6,055,000
6175908	Variable byte-length instructions using state of function bit of second byte of plurality of instructions bytes as indicative of whether first byte is a prefix byte	—	2001-01-16	$7,676,000
6151662	Data transaction typing for improved caching and prefetching characteristics	David S. Christie, Brian D. McMinn, Stephan G. Meier	2000-11-21	$5,742,000
6141745	Functional bit identifying a prefix byte via a particular state regardless of type of instruction	—	2000-10-31	$4,395,000