Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Brian S. Morris — 43 Patents

Intel: 32 patents #1,151 of 30,777Top 4%
FEFedex Supply Chain Logistics & Electronics: 4 patents #10 of 17Top 60%
Microsoft: 3 patents #13,486 of 40,388Top 35%
Honeywell: 1 patents #14,778 of 16,504Top 90%
Santa Clara, CA: #285 of 9,301 inventorsTop 4%
California: #10,282 of 386,348 inventorsTop 3%
Overall (All Time): #69,380 of 4,157,543Top 2%
43 Patents All Time
Brian S. Morris has been granted 43 US patents while listed as an inventor at Intel. The first was granted in 2006 and the most recent in December 2025. Brian S. Morris ranks #69,380 of 4,157,543 US inventors in our database (top 1.7%). Patent records list Brian S. Morris in Santa Clara, CA, US.

Issued Patents All Time

Showing 1–25 of 43 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12511744 Artifact segmentation and/or uniformity assessment of a gamma camera Saurav Daga, Siddhartha Saha, Timothy R. Crawford, Kausar Khan 2025-12-30
12405904 Sharing memory and I/O services between nodes Debendra Das Sharma, Robert G. Blankenship, Suresh Chittor, Kenneth C. Creta, Balint Fleischer +2 more 2025-09-02
12407764 Securely exposing an accelerator to privileged system components Joshua David Fender, Utkarsh Y. Kakaiya, Mohan Nair, Pratik M. Marolia 2025-09-02
12399832 Shared buffered memory routing Debendra Das Sharma, Michelle C. Jen 2025-08-26
12252891 Deck fasteners alignment tool 2025-03-18
12254061 Apparatuses and methods to accelerate matrix multiplication Maciej Urbanski, Brian J. Hickmann, Michael Rotzin, Krishnakumar Narayanan Nair, Andrew Yang +1 more 2025-03-18
12205035 Artificial neural network training using flexible floating point tensors Krishnakumar Narayanan Nair, Andrew Yang 2025-01-21
11755486 Shared buffered memory routing Debendra Das Sharma, Michelle C. Jen 2023-09-12 $19,004,000
11227383 System and method for automated cosmetic inspection of electronic devices Clark Humphrey 2022-01-18
11113196 Shared buffered memory routing Debendra Das Sharma, Michelle C. Jen 2021-09-07 $31,495,000
10915468 Sharing memory and I/O services between nodes Debendra Das Sharma, Robert G. Blankenship, Suresh Chittor, Kenneth C. Creta, Balint Fleischer +2 more 2021-02-09 $44,388,000
10762244 Securely exposing an accelerator to privileged system components Joshua David Fender, Utkarsh Y. Kakaiya, Mohan Nair, Pratik M. Marolia 2020-09-01 $24,773,000
10671740 Supporting configurable security levels for memory address ranges Binata Bhattacharyya, Raghunandan Makaram, Amy L. Santoni, George Z. Chrysos, Simon P. Johnson +1 more 2020-06-02 $32,838,000
10579464 Method and apparatus for partial cache line sparing Debaleena Das, Rajat Agarwal 2020-03-03 $18,388,000
10402964 System and method for automated cosmetic inspection of electronic devices Clark Humphrey 2019-09-03
10360096 Error handling in transactional buffered memory Bill Nale, Robert G. Blankenship, Eric L. Hendrickson 2019-07-23 $32,139,000
10198379 Early identification in transactional buffered memory Bill Nale, Robert G. Blankenship, Jeffrey C. Swanson 2019-02-05 $24,217,000
10184882 System and method for providing user guidance for electronic device processing Clark Humphrey, Joel McCarty 2019-01-22
10169858 System and method for automated cosmetic inspection of electronic devices Clark Humphrey 2019-01-01
10163508 Supporting multiple memory types in a memory slot Woojong Han, Mohamed Arafa, Mani N. Prakash, James K. Pickett, John K. Grooms +3 more 2018-12-25
10102886 Techniques for probabilistic dynamic random access memory row repair John H. Crawford, Sreenivas Mandava, Raj K. Ramanujan 2018-10-16 $21,459,000
10061719 Packed write completions Jeffrey C. Swanson, Bill Nale, Robert G. Blankenship, Jeff Willey, Eric L. Hendrickson 2018-08-28 $28,989,000
10042562 Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device Vedaraman Geetha, Henk G. Neefs, Sreenivas Mandava, Massimo Sutera 2018-08-07 $25,284,000
10031861 Protect non-memory encryption engine (non-mee) metadata in trusted execution environment Siddhartha Chhabra, Binata Bhattacharyya, Raghunandan Makaram 2018-07-24 $23,531,000
10007606 Implementation of reserved cache slots in computing system having inclusive/non inclusive tracking and two level system memory Vedaraman Geetha, Binata Bhattacharyya, Massimo Sutera 2018-06-26 $24,418,000