Issued Patents All Time
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12197357 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2025-01-14 |
| 12189550 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2025-01-07 |
| 11899615 | Multiple dies hardware processors and methods | Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati +10 more | 2024-02-13 |
| 11899964 | Methods and systems for memory bandwidth control | Ramkumar Srinivasan, Amit Kumar, Keith Robert Pflederer, Vikas Sinha | 2024-02-13 |
| 11829637 | Methods and systems for memory bandwidth control | Ramkumar Srinivasan, Amit Kumar, Keith Robert Pflederer, Vikas Sinha | 2023-11-28 |
| 11816036 | Method and system for performing data movement operations with read snapshot and in place write update | Anil Vasudevan, Venkata Krishnan, Andrew J. Herdrich, Ren Wang, Robert G. Blankenship +7 more | 2023-11-14 |
| 11789645 | Methods and systems for memory bandwidth control | Ramkumar Srinivasan, Amit Kumar, Keith Robert Pflederer, Vikas Sinha | 2023-10-17 |
| 11741030 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2023-08-29 |
| 11741028 | Efficiently striping ordered PCIe writes across multiple socket-to-socket links | Keith Robert Pflederer | 2023-08-29 |
| 11669454 | Hybrid directory and snoopy-based coherency to reduce directory update overhead in two-level memory | Jeffrey Baxter, Sai Prashanth Muralidhara, Sharada Venkateswaran, Daniel W. Liu, Nishant Singh +2 more | 2023-06-06 |
| 11586579 | Multiple dies hardware processors and methods | Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati +10 more | 2023-02-21 |
| 11327894 | Method and system for performing data movement operations with read snapshot and in place write update | Anil Vasudevan, Venkata Krishnan, Andrew J. Herdrich, Ren Wang, Robert G. Blankenship +7 more | 2022-05-10 |
| 11294852 | Multiple dies hardware processors and methods | Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati +10 more | 2022-04-05 |
| 11269793 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2022-03-08 |
| 10795853 | Multiple dies hardware processors and methods | Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati +10 more | 2020-10-06 |
| 10782729 | Clock signal modulation for processors | Bahaa Fahim, Don Soltis, Samuel D. Strom, Jason Crop | 2020-09-22 |
| 10606755 | Method and system for performing data movement operations with read snapshot and in place write update | Anil Vasudevan, Venkata Krishnan, Andrew J. Herdrich, Ren Wang, Robert G. Blankenship +7 more | 2020-03-31 |
| 10514990 | Mission-critical computing architecture | Bahaa Fahim, Swadesh Choudhary, Rahul Pal | 2019-12-24 |
| 10379768 | Selective memory mode authorization enforcement | Mahesh S. Natu | 2019-08-13 |
| 10248591 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2019-04-02 |
| 10204049 | Value of forward state by increasing local caching agent forwarding | Jeffrey D. Chamberlain, Sailesh Kottapalli, Ganesh Kumar, Henk G. Neefs, Neil Achtman +1 more | 2019-02-12 |
| 10140213 | Two level memory full line writes | Robert G. Blankenship, Jeffrey D. Chamberlain, Yen-Cheng Liu | 2018-11-27 |
| 10042562 | Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device | Henk G. Neefs, Brian S. Morris, Sreenivas Mandava, Massimo Sutera | 2018-08-07 |
| 10007606 | Implementation of reserved cache slots in computing system having inclusive/non inclusive tracking and two level system memory | Brian S. Morris, Binata Bhattacharyya, Massimo Sutera | 2018-06-26 |
| 9747041 | Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device | Henk G. Neefs, Brian S. Morris, Sreenivas Mandava, Massimo Sutera | 2017-08-29 |