Sreenivas Mandava — 13 Patents at Intel

Sreenivas Mandava has been granted 13 US patents while listed as an inventor at Intel. The first was granted in 2016 and the most recent in September 2025. Sreenivas Mandava ranks #362,438 of 4,157,543 US inventors in our database (top 8.7%). Patent records list Sreenivas Mandava in Los Altos, CA, US.

Issued Patents All Time

Showing 1–13 of 13 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
12417042	Detection of data corruption in memory address decode circuitry	Jing Ling	2025-09-16
12347507	Method and apparatus for memory chip row hammer threat backpressure signal and host side response	Kuljit S. Bains, Bill Nale, Jongwon Lee	2025-07-01
12321622	Deferred ECC (error checking and correction) memory initialization by memory scrub hardware	John V. Lovelace	2025-06-03
12235720	Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS)	Rajat Agarwal, Hsing-Min Chen, Wei-Pin Chen, Wei Wu, Jing Ling +7 more	2025-02-25
12099388	Temperature-based runtime variability in victim address selection for probabilistic schemes for row hammer	Anders Fogh	2024-09-24	$33,787,000
10552643	Fast boot up memory controller	John V. Lovelace, Debaleena Das	2020-02-04	$21,361,000
10162761	Apparatus and method for system physical address to memory module address translation	Ashok Raj, Sarathy Jayakumar, Mohan J. Kumar, Theodros Yigzaw, Ronald N. Story	2018-12-25
10102886	Techniques for probabilistic dynamic random access memory row repair	John H. Crawford, Brian S. Morris, Raj K. Ramanujan	2018-10-16	$21,459,000
10042562	Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device	Vedaraman Geetha, Henk G. Neefs, Brian S. Morris, Massimo Sutera	2018-08-07	$25,284,000
9824754	Techniques for determining victim row addresses in a volatile memory	Brian S. Morris, Suneeta Sah, Roy M. Stevens, Ted Rossin, Mathew W. Stefaniw +1 more	2017-11-21	$11,290,000
9747041	Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device	Vedaraman Geetha, Henk G. Neefs, Brian S. Morris, Massimo Sutera	2017-08-29	$8,286,000
9449671	Techniques for probabilistic dynamic random access memory row repair	John H. Crawford, Brian S. Morris, Raj K. Ramanujan	2016-09-20	$10,814,000
9269436	Techniques for determining victim row addresses in a volatile memory	Brian S. Morris, Suneeta Sah, Roy M. Stevens, Ted Rossin, Mathew W. Stefaniw +1 more	2016-02-23	$10,383,000

Sreenivas Mandava — 13 Patents

Issued Patents All Time

Patent Widget