Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9824754 | Techniques for determining victim row addresses in a volatile memory | Sreenivas Mandava, Brian S. Morris, Suneeta Sah, Ted Rossin, Mathew W. Stefaniw +1 more | 2017-11-21 |
| 9269436 | Techniques for determining victim row addresses in a volatile memory | Sreenivas Mandava, Brian S. Morris, Suneeta Sah, Ted Rossin, Mathew W. Stefaniw +1 more | 2016-02-23 |
| 6745292 | Apparatus and method for selectively allocating cache lines in a partitioned cache shared by multiprocessors | — | 2004-06-01 |
| 6078965 | Transmission line system for printed circuits | Richard Mellitz | 2000-06-20 |
| 6078997 | Directory-based coherency system for maintaining coherency in a dual-ported memory system | Gene F. Young, Larry C. James | 2000-06-20 |
| 6047316 | Multiprocessor computing apparatus having spin lock fairness | Richard R. Barton, Arthur F. Cochcroft, Jr., Edward A. McDonald, Robert J. Miller, Byron L. Reams +1 more | 2000-04-04 |
| 5860120 | Directory-based coherency system using two bits to maintain coherency on a dual ported memory system | Gene F. Young, Larry C. James | 1999-01-12 |
| 5848434 | Method and apparatus for caching state information within a directory-based coherency memory system | Gene F. Young, Larry C. James | 1998-12-08 |
| 5809536 | Method for reducing the number of coherency cycles within a directory-based cache coherency memory system uitilizing a memory state cache | Gene F. Young, Larry C. James | 1998-09-15 |