Massimo Sutera — 14 Patents at Intel

Massimo Sutera has been granted 14 US patents while listed as an inventor at Intel. The first was granted in 2004 and the most recent in November 2025. Massimo Sutera ranks #332,869 of 4,157,543 US inventors in our database (top 8.0%). Patent records list Massimo Sutera in Sunnyvale, CA, US.

Issued Patents All Time

Showing 1–14 of 14 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
12474848	Techniques for memory resource control using memory resource partitioning and monitoring	Raymond S. Tetrick, Nagi Aboulenein, Shivnandan Kaushik	2025-11-18
12451206	Extending functionality of memory controllers using a loopback mode for testing in a processor-based device	Ravi Shankar Kumar, Kha Minh Huynh, Sandeep Brahmadathan, Anil Kumar Handenahalli Rajanna, Nagi Aboulenein	2025-10-21
12314130	Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilization	Nagi Aboulenein, Sandeep Brahmadathan	2025-05-27
12204410	Integrated error correction code (ECC) and parity protection in memory control circuits for increased memory utilization	Nagi Aboulenein, Sandeep Brahmadathan	2025-01-21
12159056	Extending functionality of memory controllers in a processor-based device	Sandeep Brahmadathan, Nagi Aboulenein, Brian Thomas Chase, James Edward Casteel, Kha Minh Huynh +1 more	2024-12-03
11934263	Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilization	Nagi Aboulenein, Sandeep Brahmadathan	2024-03-19
10162750	System address reconstruction	—	2018-12-25
10042562	Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device	Vedaraman Geetha, Henk G. Neefs, Brian S. Morris, Sreenivas Mandava	2018-08-07	$25,284,000
10007606	Implementation of reserved cache slots in computing system having inclusive/non inclusive tracking and two level system memory	Vedaraman Geetha, Brian S. Morris, Binata Bhattacharyya	2018-06-26	$24,418,000
9747041	Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device	Vedaraman Geetha, Henk G. Neefs, Brian S. Morris, Sreenivas Mandava	2017-08-29	$8,286,000
9734054	Efficient implementation of geometric series	—	2017-08-15	$8,272,000
7721011	Method and apparatus for reordering memory accesses to reduce power consumption in computer systems	—	2010-05-18	$28,432,000
6900674	Method and circuitry for phase align detection in multi-clock domain	Fabrizio Romano, David A. Bunsey, Jr., Daniel Cheung, Lan Lee, Kevin Normoyle +2 more	2005-05-31	$6,322,000
6832180	Method for reducing noise in integrated circuit layouts	Alan Smith	2004-12-14	$14,930,000

Massimo Sutera — 14 Patents

Issued Patents All Time

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