Issued Patents All Time
Showing 25 most recent of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12360918 | Memory pools in a memory model for a unified computing system | Anthony Asaro, Mark Hummel | 2025-07-15 |
| 11741019 | Memory pools in a memory model for a unified computing system | Anthony Asaro, Mark Hummel | 2023-08-29 |
| 11119944 | Memory pools in a memory model for a unified computing system | Anthony Asaro, Mark Hummel | 2021-09-14 |
| 10324860 | Memory heaps in a memory model for a unified computing system | Anthony Asaro, Mark Hummel | 2019-06-18 |
| 9965392 | Managing coherent memory between an accelerated processing device and a central processing unit | Anthony Asaro, Mark Hummel | 2018-05-08 |
| 9448930 | Memory heaps in a memory model for a unified computing system | Anthony Asaro, Mark Hummel | 2016-09-20 |
| 9430391 | Managing coherent memory between an accelerated processing device and a central processing unit | Anthony Asaro, Mark Hummel | 2016-08-30 |
| 9116809 | Memory heaps in a memory model for a unified computing system | Anthony Asaro, Mark Hummel | 2015-08-25 |
| 9009419 | Shared memory space in a unified memory model | Anthony Asaro, Mark Hummel, Mark Fowler | 2015-04-14 |
| 8984511 | Visibility ordering in a memory model for a unified computing system | Anthony Asaro, Mark Hummel | 2015-03-17 |
| 8935475 | Cache management for memory operations | Anthony Asaro, Mark Hummel, Norman Rubin, Mark Fowler | 2015-01-13 |
| 8099651 | Subsystem and method for encoding 64-bit data nibble error correct and cyclic-redundancy code (CRC) address error detect for use in a 76-bit memory module | Robert Hathaway | 2012-01-17 |
| 7552302 | Ordering operation | Gil Tene, Jack Choquette, David Kruckernyer, Cliff N. Click, Jr. | 2009-06-23 |
| 7437597 | Write-back cache with different ECC codings for clean and dirty lines with refetching of uncorrectable clean lines | David A. Kruckemyer, Jack Choquette | 2008-10-14 |
| 7398449 | Encoding 64-bit data nibble error correct and cyclic-redundancy code (CRC) address error detect for use on a 76-bit memory module | Robert Hathaway | 2008-07-08 |
| 7376800 | Speculative multiaddress atomicity | Jack Choquette, Gil Tene | 2008-05-20 |
| 7366847 | Distributed cache coherence at scalable requestor filter pipes that accumulate invalidation acknowledgements from other requestor filter pipes using ordering messages from central snoop tag | David A. Kruckemyer, Robert Hathaway | 2008-04-29 |
| 7337339 | Multi-level power monitoring, filtering and throttling at local blocks and globally | Jack Choquette, Elias M. ATMEH, Scott D. Sellers, Murali Sundaresan, Manuel Gautho | 2008-02-26 |
| 7332929 | Wide-scan on-chip logic analyzer with global trigger and interleaved SRAM capture buffers | Sreenivas Aerra Reddy, John Phillips | 2008-02-19 |
| 7203890 | Address error detection by merging a polynomial-based CRC code of address bits with two nibbles of data or data ECC bits | — | 2007-04-10 |
| 7143304 | Method and apparatus for enhancing the speed of a synchronous bus | Sharath Raghava, Christopher Furman | 2006-11-28 |
| 6900674 | Method and circuitry for phase align detection in multi-clock domain | Fabrizio Romano, David A. Bunsey, Jr., Daniel Cheung, Lan Lee, Sung-Hun Oh +2 more | 2005-05-31 |
| 6553435 | DMA transfer method for a system including a single-chip processor with a processing core and a device interface in different clock domains | Michael A. Csoppenszky, Jaybharat Boddu, Jui-Cheng Su, Alex S. Han, Rajasekhar Cherabuddi +1 more | 2003-04-22 |
| 6535966 | System and method for using a page tracking buffer to reduce main memory latency in a computer system | Rajasekhar Cherabuddi, Brian J. McGee | 2003-03-18 |
| 6496917 | Method to reduce memory latencies by performing two levels of speculation | Rajasekhar Cherabuddi, Brian J. McGee, Meera Kasinathan, Anup K. Sharma, Sutikshan Bhutani | 2002-12-17 |