Issued Patents All Time
Showing 26–50 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6477622 | Simplified writeback handling | Meera Kasinathan, Rajasekhar Cherabuddi | 2002-11-05 |
| 6446168 | Method and apparatus for dynamically switching a cache between direct-mapped and 4-way set associativity | Bruce E. Petrick | 2002-09-03 |
| 6100732 | Phase enable and clock generation circuit | David A. Penry | 2000-08-08 |
| 5987081 | Method and apparatus for a testable high frequency synchronizer | Michael A. Csoppenszky, Prakash Narain | 1999-11-16 |
| 5907485 | Method and apparatus for flow control in packet-switched computer system | William C. Van Loo, Zahir Ebrahim, Satyanarayana Nishtala, Leslie D. Kohn, Louis F. Coffin, III | 1999-05-25 |
| 5905998 | Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system | Zahir Ebrahim, Satyanarayana Nishtala, William C. Van Loo, Paul N. Loewenstein, Louis F. Coffin, III | 1999-05-18 |
| 5894587 | Multiple bus bridge system for maintaining a complete order by delaying servicing interrupts while posting write requests | David A. Penry, Jui-Cheng Su | 1999-04-13 |
| 5893153 | Method and apparatus for preventing a race condition and maintaining cache coherency in a processor with integrated cache memory and input/output control | Tzungren Allan Tzeng | 1999-04-06 |
| 5892957 | Method and apparatus for interrupt communication in packet-switched microprocessor-based computer system | Zahir Ebrahim, Satyanarayana Nishtala, William C. Van Loo, Sun Den Chen, Charles E. Narad | 1999-04-06 |
| 5884100 | Low-latency, high-throughput, integrated cache coherent I/O system for a single-chip processor | Michael A. Csoppenszky, Jaybharat Boddu, Jui-Cheng Su, Alex S. Han, Rajasekhar Cherabuddi +1 more | 1999-03-16 |
| 5862356 | Pipelined distributed bus arbitration system | Zahir Ebrahim, Satyanarayana Nishtala, William C. Van Loo, Louis F. Coffin, III | 1999-01-19 |
| 5852608 | Structure and method for bi-directional data transfer between asynchronous clock domains | Michael A. Csoppenszky | 1998-12-22 |
| 5761708 | Apparatus and method to speculatively initiate primary memory accesses | Rajasekhar Cherabuddi, Anuradha N. Moudgal | 1998-06-02 |
| 5737755 | System level mechanism for invalidating data stored in the external cache of a processor in a computer system | Zahir Ebrahim, Satyanarayana Nishtala, William C. Van Loo, Leslie D. Kohn, Louis F. Coffin, III | 1998-04-07 |
| 5710891 | Pipelined distributed bus arbitration system | Zahir Ebrahim, Satyanarayana Nishtala, William C. Van Loo, Louis F. Coffin, III | 1998-01-20 |
| 5706463 | Cache coherent computer system that minimizes invalidation and copyback operations | Zahir Ebrahim, Satyanarayana Nishtala, William Loo, Leslie D. Kohn, Louis F. Coffin, III | 1998-01-06 |
| 5692197 | Method and apparatus for reducing power consumption in a computer network without sacrificing performance | Charles E. Narad, Zahir Ebrahim, Satyanarayana Nishtala, William C. Van Loo, Louis F. Coffin, III +1 more | 1997-11-25 |
| 5689713 | Method and apparatus for interrupt communication in a packet-switched computer system | Zahir Ebrahim, Satyanarayana Nishtala, William C. Van Loo, Sun Den Chen, Charles E. Narad | 1997-11-18 |
| 5684977 | Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system | William C. Van Loo, Zahir Ebrahim, Satyanarayana Nishtala, Paul N. Loewenstein, Louis F. Coffin, III | 1997-11-04 |
| 5657472 | Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor | William C. Van Loo, Zahir Ebrahim, Satyanarayana Nishtala, Leslie D. Kohn, Louis F. Coffin, III +1 more | 1997-08-12 |
| 5655100 | Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system | Zahir Ebrahim, Satyanarayana Nishtala, William C. Van Loo, Paul N. Loewenstein, Louis F. Coffin, III | 1997-08-05 |
| 5644753 | Fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system | Zahir Ebrahim, Satyanarayana Nishtala, William C. Van Loo | 1997-07-01 |
| 5634068 | Packet switched cache coherent multiprocessor system | Satyanarayana Nishtala, Zahir Ebrahim, William C. Van Loo, Leslie D. Kohn, Louis F. Coffin, III | 1997-05-27 |
| 5070475 | Floating point unit interface | James Guyer, Rainer Vogt, Anthony S. Fong | 1991-12-03 |
| 4949247 | System for transferring multiple vector data elements to and from vector memory in a single operation | R. Ashley Stephenson | 1990-08-14 |