Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9021186 | Partial allocate paging mechanism using a controller and a buffer | — | 2015-04-28 |
| 9015420 | Mitigate flash write latency and bandwidth limitation by preferentially storing frequently written sectors in cache memory during a databurst | — | 2015-04-21 |
| 8756376 | Mitigate flash write latency and bandwidth limitation with a sector-based write activity log | — | 2014-06-17 |
| 8745311 | Flash memory usability enhancements in main memory application | — | 2014-06-03 |
| 8738840 | Operating system based DRAM/FLASH management scheme | — | 2014-05-27 |
| 8719489 | Hardware based wear leveling mechanism for flash memory using a free list | — | 2014-05-06 |
| 8560761 | Memory resource management for a flash aware kernel | — | 2013-10-15 |
| 8458393 | Flash memory and operating system kernel | — | 2013-06-04 |
| 8352671 | Partial allocate paging mechanism using a controller and a buffer | — | 2013-01-08 |
| 8332572 | Wear leveling mechanism using a DRAM buffer | — | 2012-12-11 |
| 8275945 | Mitigation of flash memory latency and bandwidth limitations via a write activity log and buffer | — | 2012-09-25 |
| 8209463 | Expansion slots for flash memory based random access memory subsystem | — | 2012-06-26 |
| 7733130 | Skew tolerant communication between ratioed synchronous clocks | Mahmudul Hassan | 2010-06-08 |
| 6813626 | Method and apparatus for performing fused instructions by determining exponent differences | Choon Ping Chng | 2004-11-02 |
| 6751644 | Method and apparatus for elimination of inherent carries | Choon Ping Chng | 2004-06-15 |
| 6647404 | Double precision floating point multiplier having a 32-bit booth-encoded array multiplier | Choon Ping Chng | 2003-11-11 |
| 6553435 | DMA transfer method for a system including a single-chip processor with a processing core and a device interface in different clock domains | Kevin Normoyle, Michael A. Csoppenszky, Jaybharat Boddu, Jui-Cheng Su, Alex S. Han +1 more | 2003-04-22 |
| 6446104 | Double precision floating point multiplier having a 32-bit booth-encoded array multiplier | Choon Ping Chng | 2002-09-03 |
| 6385678 | Method and apparatus for bus arbitration with weighted bandwidth allocation | Eino Jacobs | 2002-05-07 |
| 5893153 | Method and apparatus for preventing a race condition and maintaining cache coherency in a processor with integrated cache memory and input/output control | Kevin Normoyle | 1999-04-06 |
| 5884100 | Low-latency, high-throughput, integrated cache coherent I/O system for a single-chip processor | Kevin Normoyle, Michael A. Csoppenszky, Jaybharat Boddu, Jui-Cheng Su, Alex S. Han +1 more | 1999-03-16 |