Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9569220 | Processor branch cache with secondary branches | — | 2017-02-14 |
| 9465616 | Instruction cache with way prediction | — | 2016-10-11 |
| 8583895 | Compressed instruction format for use in a VLIW processor | Michael A. Ang | 2013-11-12 |
| 6704859 | Compressed instruction format for use in a VLIW processor | Michael A. Ang | 2004-03-09 |
| 6385678 | Method and apparatus for bus arbitration with weighted bandwidth allocation | Tzungren Allan Tzeng | 2002-05-07 |
| 6134633 | Prefetch management in cache memory | — | 2000-10-17 |
| 6131152 | Planar cache layout and instruction stream therefor | Michael A. Ang | 2000-10-10 |
| 6047358 | Computer system, cache memory and process for cache entry replacement with selective locking of elements in different ways and groups | — | 2000-04-04 |
| 5931939 | Read crossbar elimination in a VLIW processor | — | 1999-08-03 |
| 5909563 | Computer system including an interface for transferring data between two clock domains | — | 1999-06-01 |
| 5878267 | Compressed instruction format for use in a VLIW processor and processor for processing such instructions | Hari Hampapuram, Yen Lee, Michael A. Ang | 1999-03-02 |
| 5862398 | Compiler generating swizzled instructions usable in a simplified cache layout | Hari Hampapuram, Yen Lee, Michael A. Ang | 1999-01-19 |
| 5852741 | VLIW processor which processes compressed instruction format | Michael A. Ang | 1998-12-22 |
| 5826054 | Compressed Instruction format for use in a VLIW processor | Michael A. Ang | 1998-10-20 |
| 5787302 | Software for producing instructions in a compressed format for a VLIW processor | Hari Hampapuram, Yen Lee, Michael A. Ang | 1998-07-28 |
| 5444288 | CMOS integrated circuit having improved power-supply filtering | — | 1995-08-22 |