Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6381664 | System for multisized bus coupling in a packet-switched computer system | Satyanarayana Nishtala, William C. Van Loo | 2002-04-30 |
| 6154777 | System for context-dependent name resolution | — | 2000-11-28 |
| 6101565 | System for multisized bus coupling in a packet-switched computer system | Satyanarayana Nishtala, William C. Van Loo | 2000-08-08 |
| 5987557 | Method and apparatus for implementing hardware protection domains in a system with no memory management unit (MMU) | — | 1999-11-16 |
| 5987579 | Method and apparatus for quickly initiating memory accesses in a multiprocessor cache coherent computer system | Satyanarayana Nishtala, William C. Van Loo, Raymond Ng, Louis F. Coffin, III | 1999-11-16 |
| 5970505 | Linking related data in a document set including a plurality of books written by different groups of authors in a computer network | — | 1999-10-19 |
| 5930807 | Apparatus and method for fast filtering read and write barrier operations in garbage collection system | Sanjay Vishin | 1999-07-27 |
| 5907485 | Method and apparatus for flow control in packet-switched computer system | William C. Van Loo, Satyanarayana Nishtala, Kevin Normoyle, Leslie D. Kohn, Louis F. Coffin, III | 1999-05-25 |
| 5905998 | Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system | Satyanarayana Nishtala, William C. Van Loo, Kevin Normoyle, Paul N. Loewenstein, Louis F. Coffin, III | 1999-05-18 |
| 5893165 | System and method for parallel execution of memory transactions using multiple memory models, including SSO, TSO, PSO and RMO | — | 1999-04-06 |
| 5893121 | System and method for swapping blocks of tagged stack entries between a tagged stack cache and an untagged main memory storage | Ahmed Mohamed | 1999-04-06 |
| 5892957 | Method and apparatus for interrupt communication in packet-switched microprocessor-based computer system | Kevin Normoyle, Satyanarayana Nishtala, William C. Van Loo, Sun Den Chen, Charles E. Narad | 1999-04-06 |
| 5887134 | System and method for preserving message order while employing both programmed I/O and DMA operations | — | 1999-03-23 |
| 5878264 | Power sequence controller with wakeup logic for enabling a wakeup interrupt handler procedure | — | 1999-03-02 |
| 5862356 | Pipelined distributed bus arbitration system | Kevin Normoyle, Satyanarayana Nishtala, William C. Van Loo, Louis F. Coffin, III | 1999-01-19 |
| 5848423 | Garbage collection system and method for locating root set pointers in method activation records | Ahmed Mohamed | 1998-12-08 |
| 5737755 | System level mechanism for invalidating data stored in the external cache of a processor in a computer system | Satyanarayana Nishtala, William C. Van Loo, Kevin Normoyle, Leslie D. Kohn, Louis F. Coffin, III | 1998-04-07 |
| 5710891 | Pipelined distributed bus arbitration system | Kevin Normoyle, Satyanarayana Nishtala, William C. Van Loo, Louis F. Coffin, III | 1998-01-20 |
| 5706463 | Cache coherent computer system that minimizes invalidation and copyback operations | Satyanarayana Nishtala, William Loo, Kevin Normoyle, Leslie D. Kohn, Louis F. Coffin, III | 1998-01-06 |
| 5692197 | Method and apparatus for reducing power consumption in a computer network without sacrificing performance | Charles E. Narad, Satyanarayana Nishtala, William C. Van Loo, Kevin Normoyle, Louis F. Coffin, III +1 more | 1997-11-25 |
| 5689713 | Method and apparatus for interrupt communication in a packet-switched computer system | Kevin Normoyle, Satyanarayana Nishtala, William C. Van Loo, Sun Den Chen, Charles E. Narad | 1997-11-18 |
| 5684977 | Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system | William C. Van Loo, Satyanarayana Nishtala, Kevin Normoyle, Paul N. Loewenstein, Louis F. Coffin, III | 1997-11-04 |
| 5657472 | Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor | William C. Van Loo, Satyanarayana Nishtala, Kevin Normoyle, Leslie D. Kohn, Louis F. Coffin, III +1 more | 1997-08-12 |
| 5655100 | Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system | Satyanarayana Nishtala, William C. Van Loo, Kevin Normoyle, Paul N. Loewenstein, Louis F. Coffin, III | 1997-08-05 |
| 5644753 | Fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system | Kevin Normoyle, Satyanarayana Nishtala, William C. Van Loo | 1997-07-01 |