Issued Patents All Time
Showing 25 most recent of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6662306 | Fast forwarding slave requests in a packet-switched computer system by transmitting request to slave in advance to avoid arbitration delay when system controller validates request | — | 2003-12-09 |
| 6597665 | System for dynamic ordering support in a ringlet serial interconnect | Satyanarayana Nishtala | 2003-07-22 |
| 6463472 | System for maintaining strongly sequentially ordered packet flow in a ring network system with busy and failed nodes | — | 2002-10-08 |
| 6381664 | System for multisized bus coupling in a packet-switched computer system | Satyanarayana Nishtala, Zahir Ebrahim | 2002-04-30 |
| 6260174 | Method and apparatus for fast-forwarding slave requests in a packet-switched computer system | — | 2001-07-10 |
| 6233615 | System for maintaining strongly sequentially ordered packet flow in a ring network system with busy and failed nodes | — | 2001-05-15 |
| 6101565 | System for multisized bus coupling in a packet-switched computer system | Satyanarayana Nishtala, Zahir Ebrahim | 2000-08-08 |
| 6065052 | System for maintaining strongly sequentially ordered packet flow in a ring network system with busy and failed nodes | — | 2000-05-16 |
| 6064672 | System for dynamic ordering support in a ringlet serial interconnect | Satyanarayana Nishtala | 2000-05-16 |
| 5987579 | Method and apparatus for quickly initiating memory accesses in a multiprocessor cache coherent computer system | Satyanarayana Nishtala, Zahir Ebrahim, Raymond Ng, Louis F. Coffin, III | 1999-11-16 |
| 5919265 | Source synchronization data transfers without resynchronization penalty | Satyanarayana Nishtala | 1999-07-06 |
| 5907485 | Method and apparatus for flow control in packet-switched computer system | Zahir Ebrahim, Satyanarayana Nishtala, Kevin Normoyle, Leslie D. Kohn, Louis F. Coffin, III | 1999-05-25 |
| 5905998 | Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system | Zahir Ebrahim, Satyanarayana Nishtala, Kevin Normoyle, Paul N. Loewenstein, Louis F. Coffin, III | 1999-05-18 |
| 5892957 | Method and apparatus for interrupt communication in packet-switched microprocessor-based computer system | Kevin Normoyle, Zahir Ebrahim, Satyanarayana Nishtala, Sun Den Chen, Charles E. Narad | 1999-04-06 |
| 5864677 | System for preserving sequential ordering and supporting nonidempotent commands in a ring network with busy nodes | — | 1999-01-26 |
| 5862356 | Pipelined distributed bus arbitration system | Kevin Normoyle, Zahir Ebrahim, Satyanarayana Nishtala, Louis F. Coffin, III | 1999-01-19 |
| 5854906 | Method and apparatus for fast-forwarding slave request in a packet-switched computer system | — | 1998-12-29 |
| 5852718 | Method and apparatus for hybrid packet-switched and circuit-switched flow control in a computer system | — | 1998-12-22 |
| 5737755 | System level mechanism for invalidating data stored in the external cache of a processor in a computer system | Zahir Ebrahim, Satyanarayana Nishtala, Kevin Normoyle, Leslie D. Kohn, Louis F. Coffin, III | 1998-04-07 |
| 5710891 | Pipelined distributed bus arbitration system | Kevin Normoyle, Zahir Ebrahim, Satyanarayana Nishtala, Louis F. Coffin, III | 1998-01-20 |
| 5692197 | Method and apparatus for reducing power consumption in a computer network without sacrificing performance | Charles E. Narad, Zahir Ebrahim, Satyanarayana Nishtala, Kevin Normoyle, Louis F. Coffin, III +1 more | 1997-11-25 |
| 5689713 | Method and apparatus for interrupt communication in a packet-switched computer system | Kevin Normoyle, Zahir Ebrahim, Satyanarayana Nishtala, Sun Den Chen, Charles E. Narad | 1997-11-18 |
| 5684977 | Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system | Zahir Ebrahim, Satyanarayana Nishtala, Kevin Normoyle, Paul N. Loewenstein, Louis F. Coffin, III | 1997-11-04 |
| 5657472 | Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor | Zahir Ebrahim, Satyanarayana Nishtala, Kevin Normoyle, Leslie D. Kohn, Louis F. Coffin, III +1 more | 1997-08-12 |
| 5655100 | Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system | Zahir Ebrahim, Satyanarayana Nishtala, Kevin Normoyle, Paul N. Loewenstein, Louis F. Coffin, III | 1997-08-05 |