Issued Patents All Time
Showing 26–32 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5644753 | Fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system | Zahir Ebrahim, Kevin Normoyle, Satyanarayana Nishtala | 1997-07-01 |
| 5634068 | Packet switched cache coherent multiprocessor system | Satyanarayana Nishtala, Zahir Ebrahim, Kevin Normoyle, Leslie D. Kohn, Louis F. Coffin, III | 1997-05-27 |
| 5581729 | Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system | Satyanarayana Nishtala, Zahir Ebrahim, Paul N. Loewenstein, Sue-Kyoung Lee, Louis F. Coffin III | 1996-12-03 |
| 5263142 | Input/output cache with mapped pages allocated for caching direct (virtual) memory access input/output data based on type of I/O devices | John E. Watkins, David Labuda | 1993-11-16 |
| 5247648 | Maintaining data coherency between a central cache, an I/O cache and a memory | John E. Watkins, David Labuda | 1993-09-21 |
| 5161162 | Method and apparatus for system bus testability through loopback | John E. Watkins, Kurt Michels, Hugh Chang | 1992-11-03 |
| 4271468 | Multiprocessor mechanism for handling channel interrupts | Neal T. Christensen, Robert H. Werner, Joseph A. Wetzel, Carl Zeitler | 1981-06-02 |