Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10935595 | Methods for identifying integrated circuit failures caused by asynchronous clock-domain crossings in the presence of multiple modes | Vishnu Vimjam, Vikas Sachdeva, Paul Vyedin | 2021-03-02 |
| 10936774 | Methods for identifying integrated circuit failures caused by reset-domain interactions | Oren Katzir, Sanjeev Mahajan, Vishnu Vimjam | 2021-03-02 |
| 6839884 | Hierarchical functional verification | Rajeev Ranjan, Christopher Morrison, John Mark Beardslee, Rajiv Kumar | 2005-01-04 |
| 6704912 | Method and apparatus for characterizing information about design attributes | Rajeev Ranjan, Christopher Morrison, John Mark Beardslee | 2004-03-09 |
| 6651228 | Intent-driven functional verification of digital designs | Rajiv Kumar, John Mark Beardslee, Rajeev Ranjan, Christopher Morrison | 2003-11-18 |
| 6571375 | Determining dependency relationships among design verification checks | Rajeev Ranjan, Christopher Morrison, John Mark Beardslee | 2003-05-27 |
| 6539523 | Automatic formulation of design verification checks based upon a language representation of a hardware design to verify the intended behavior of the hardware design | Jay Andrew Littlefield, Christopher Morrison, Rajeev Ranjan | 2003-03-25 |
| 6493852 | Modeling and verifying the intended flow of logical signals in a hardware design | Rajiv Kumar | 2002-12-10 |
| 5987081 | Method and apparatus for a testable high frequency synchronizer | Michael A. Csoppenszky, Kevin Normoyle | 1999-11-16 |
| 5740182 | Method and apparatus for testing a circuit with reduced test pattern constraints | — | 1998-04-14 |