| 9256500 |
Physical domain error isolation and recovery in a multi-domain system |
Jurgen Schulz, Vishak Chandrasekhar, Wayne F. Seltzer |
2016-02-09 |
| 8516199 |
Bandwidth-efficient directory-based coherence protocol |
Robert E. Cypher, Haakan E. Zeffer, Bharat Daga |
2013-08-20 |
| 7487327 |
Processor and method for device-specific memory address translation |
Bruce J. Chang, Ricky C. Hetherington, David M. Kahn, Ashley Saulsbury |
2009-02-03 |
| 6877077 |
Memory controller and method using read and write queues and an ordering queue for dispatching read and write memory requests out of order to reduce memory latency |
Jade B. Chau |
2005-04-05 |
| 6535966 |
System and method for using a page tracking buffer to reduce main memory latency in a computer system |
Rajasekhar Cherabuddi, Kevin Normoyle |
2003-03-18 |
| 6496917 |
Method to reduce memory latencies by performing two levels of speculation |
Rajasekhar Cherabuddi, Kevin Normoyle, Meera Kasinathan, Anup K. Sharma, Sutikshan Bhutani |
2002-12-17 |