Issued Patents All Time
Showing 1–25 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9208084 | Extended main memory hierarchy having flash memory for page fault handling | Sanjiv Kapil | 2015-12-08 |
| 8180981 | Cache coherent support for flash in a memory hierarchy | Sanjiv Kapil | 2012-05-15 |
| 7873776 | Multiple-core processor with support for multiple virtual processors | Bikram Saha | 2011-01-18 |
| 7716521 | Multiple-core, multithreaded processor with flexible error steering mechanism | Hunter S. Donahue, Jimmy Lau | 2010-05-11 |
| 7685354 | Multiple-core processor with flexible mapping of processor cores to cache banks | Manish K. Shah, Gregory F. Grohoski, Bikram Saha | 2010-03-23 |
| 7644221 | System interface unit | Paul G. Chan | 2010-01-05 |
| 7587658 | ECC encoding for uncorrectable errors | Ye Tong | 2009-09-08 |
| 7529894 | Use of FBDIMM channel as memory channel and coherence channel | Stephen E. Phillips | 2009-05-05 |
| 7487327 | Processor and method for device-specific memory address translation | Bruce J. Chang, Brian J. McGee, David M. Kahn, Ashley Saulsbury | 2009-02-03 |
| 7401206 | Apparatus and method for fine-grained multithreading in a multipipelined processor core | Gregory F. Grohoski, Robert T. Golla | 2008-07-15 |
| 7398360 | Multi-socket symmetric multiprocessing (SMP) system for chip multi-threaded (CMT) processors | Stephen E. Phillips | 2008-07-08 |
| 7370243 | Precise error handling in a fine grain multithreaded multicore processor | Gregory F. Grohoski, Paul J. Jordan, Robert M. Maier | 2008-05-06 |
| 7353340 | Multiple independent coherence planes for maintaining coherency | Stephen E. Phillips | 2008-04-01 |
| 7330988 | Method and apparatus for power throttling in a multi-thread processor | Robert T. Golla | 2008-02-12 |
| 7240160 | Multiple-core processor with flexible cache directory scheme | Bikram Saha | 2007-07-03 |
| 6684299 | Method for operating a non-blocking hierarchical cache throttle | Thomas M. Wicki | 2004-01-27 |
| 6484240 | Mechanism for reordering transactions in computer systems with snoop-based cache consistency protocols | Robert E. Cypher, Belliappa Kuttanna | 2002-11-19 |
| 6430654 | Apparatus and method for distributed non-blocking multi-level cache | Sharad Mehrotra | 2002-08-06 |
| 6360285 | Apparatus for determining memory bank availability in a computer system | David Fenwick, Denis Foley, David W. Hartwell, Dale R. Keck, Elbert Bloom | 2002-03-19 |
| 6353877 | Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line write | Samuel H. Duncan, Glenn Arthur Herdeg, Craig D. Keefer, Maurice B. Steinman, Paul Michael Guglielmi | 2002-03-05 |
| 6327667 | Apparatus and method for operating clock sensitive devices in multiple timing domains | Peter J. Bannon | 2001-12-04 |
| 6269426 | Method for operating a non-blocking hierarchical cache throttle | Thomas M. Wicki | 2001-07-31 |
| 6240502 | Apparatus for dynamically reconfiguring a processor | Ramesh Panwar | 2001-05-29 |
| 6219723 | Method and apparatus for moderating current demand in an integrated circuit processor | Ramesh Panwar | 2001-04-17 |
| 6212602 | Cache tag caching | Thomas M. Wicki, Meera Kasinathan | 2001-04-03 |