Issued Patents All Time
Showing 26–50 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6154815 | Non-blocking hierarchical cache throttle | Thomas M. Wicki | 2000-11-28 |
| 6154812 | Method for inhibiting thrashing in a multi-level non-blocking cache system | Sharad Mehrotra, Ramesh Panwar | 2000-11-28 |
| 6148371 | Multi-level non-blocking cache system with inhibiting thrashing | Sharad Mehrotra, Ramesh Panwar | 2000-11-14 |
| 6145054 | Apparatus and method for handling multiple mergeable misses in a non-blocking cache | Sharad Mehrotra, Michelle Wong | 2000-11-07 |
| 6128711 | Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line writes | Samuel H. Duncan, Glenn Arthur Herdeg, Craig D. Keefer, Maurice B. Steinman, Paul Michael Guglielmi | 2000-10-03 |
| 6122709 | Cache with reduced tag information storage | Thomas M. Wicki, Meera Kasinathan | 2000-09-19 |
| 6119205 | Speculative cache line write backs to avoid hotspots | Thomas M. Wicki, Meera Kasinathan, Fong Pong | 2000-09-12 |
| 6081873 | In-line bank conflict detection and resolution in a multi-ported non-blocking cache | Sharad Mehrotra, Ramesh Panwar | 2000-06-27 |
| 6076129 | Distributed data bus sequencing for a system bus with separate address and data bus protocols | David Fenwick, Denis Foley, Stephen R. Van Doren, David W. Hartwell, Elbert Bloom | 2000-06-13 |
| 6073212 | Reducing bandwidth and areas needed for non-inclusive memory hierarchy by using dual tags | Norman M. Hayes, Belliappa Kuttanna, Krishna M. Thatipelli, Fong Pong | 2000-06-06 |
| 6058472 | Apparatus for maintaining program correctness while allowing loads to be boosted past stores in an out-of-order machine | Ramesh Panwar, P. Chidambaran | 2000-05-02 |
| 6052775 | Method for non-intrusive cache fills and handling of load misses | Ramesh Panwar | 2000-04-18 |
| 6006326 | Apparatus for restraining over-eager load boosting in an out-of-order machine using a memory disambiguation buffer for determining dependencies | Ramesh Panwar | 1999-12-21 |
| 5999727 | Method for restraining over-eager load boosting using a dependency color indicator stored in cache with both the load and store instructions | Ramesh Panwar | 1999-12-07 |
| 5996048 | Inclusion vector architecture for a level two cache | Rajasekhar Cherabuddi | 1999-11-30 |
| 5987594 | Apparatus for executing coded dependent instructions having variable latencies | Ramesh Panwar | 1999-11-16 |
| 5978864 | Method for thermal overload detection and prevention for an intergrated circuit processor | Ramesh Panwar | 1999-11-02 |
| 5948106 | System for thermal overload detection and prevention for an integrated circuit processor | Ramesh Panwar | 1999-09-07 |
| 5930819 | Method for performing in-line bank conflict detection and resolution in a multi-ported non-blocking cache | Sharad Mehrotra, Ramesh Panwar | 1999-07-27 |
| 5909697 | Reducing cache misses by snarfing writebacks in non-inclusive memory systems | Norman M. Hayes, Belliappa Kuttanna, Fong Pong, Krishna M. Thatipelli | 1999-06-01 |
| 5890008 | Method for dynamically reconfiguring a processor | Ramesh Panwar | 1999-03-30 |
| 5666551 | Distributed data bus sequencing for a system bus with separate address and data bus protocols | David Fenwick, Denis Foley, Stephen R. Van Doren, David W. Hartwell, Elbert Bloom | 1997-09-09 |
| 5475690 | Delay compensated signal propagation | Douglas J. Burns, David Fenwick | 1995-12-12 |
| 5349651 | System for translation of virtual to physical addresses by operating memory management processor for calculating location of physical address in memory concurrently with cache comparing virtual addresses for translation | David A. Webb, David B. Fite, Jr., John E. Murray, Tryggve Fossum, Dwight P. Manley | 1994-09-20 |
| 5285323 | Integrated circuit chip having primary and secondary random access memories for a hierarchical cache | Francis X. McKeen, Joseph D. Marci, Tryggve Fossum, Joel S. Emer | 1994-02-08 |