Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7463625 | Stackable switch port collapse mechanism | Ronald M. Salett, Nicholas Ilyadis | 2008-12-09 |
| 6496502 | Distributed multi-link trunking method and apparatus | Nicholas Ilyadis, Ronald M. Salett | 2002-12-17 |
| 6490276 | Stackable switch port collapse mechanism | Ronald M. Salett, Nicholas Ilyadis | 2002-12-03 |
| 6252888 | Method and apparatus providing network communications between devices using frames with multiple formats | Nicholas Ilyadis, Ronald M. Salett | 2001-06-26 |
| 6226290 | Method and apparatus for adjusting an interpacket gap using a network device in a data communications network | Ronald M. Salett, Nicholas Ilyadis | 2001-05-01 |
| 6061737 | Two-pin distributed ethernet bus architecture | Elaine H. Fite, Ron Salett | 2000-05-09 |
| 5963719 | Two-pin distributed ethernet bus architecture | Elaine H. Fite, Ron Salett | 1999-10-05 |
| 5619662 | Memory reference tagging | Simon C. Steely, Jr., David J. Sager | 1997-04-08 |
| 5519841 | Multi instruction register mapper | David J. Sager, Simon C. Steely, Jr. | 1996-05-21 |
| 5349651 | System for translation of virtual to physical addresses by operating memory management processor for calculating location of physical address in memory concurrently with cache comparing virtual addresses for translation | Ricky C. Hetherington, David A. Webb, John E. Murray, Tryggve Fossum, Dwight P. Manley | 1994-09-20 |
| 5167026 | Simultaneously or sequentially decoding multiple specifiers of a variable length pipeline instruction based on detection of modified value of specifier registers | John E. Murray, Mark A. Firstenberg, Lawrence O. Herman, Ronald M. Salett | 1992-11-24 |
| 5151867 | Method of minimizing sum-of-product cases in a heterogeneous data base environment for circuit synthesis | Donald F. Hooper, James L. Finnerty, Snehamay Kundu | 1992-09-29 |
| 5148528 | Method and apparatus for simultaneously decoding three operands in a variable length instruction when one of the operands is also of variable length | John E. Murray, Tryggve Fossum | 1992-09-15 |
| 5142634 | Branch prediction | John E. Murray, Dwight P. Manley, Michael M. McKeon, Elaine H. Fite, Ronald M. Salett +1 more | 1992-08-25 |
| 5142633 | Preprocessing implied specifiers in a pipelined processor | John E. Murray, Mark A. Firstenberg | 1992-08-25 |
| 5142631 | System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register | John E. Murray, Mark A. Firstenberg, Michael M. McKeon, Wiliam R. Grundmann, David A. Webb +4 more | 1992-08-25 |
| 5125083 | Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system | Tryggve Fossum, Ricky C. Hetherington, John E. Murray, Jr. David A. Webb | 1992-06-23 |
| 5113515 | Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer | Ricky C. Hetherington, Michael M. McKeon, Dwight P. Manley, John E. Murray | 1992-05-12 |
| 5109495 | Method and apparatus using a source operand list and a source operand pointer queue between the execution unit and the instruction decoding and operand processing units of a pipelined data processor | Tryggve Fossum, William R. Grundmann, Dwight P. Manely, Francis X. McKeen, John E. Murray +3 more | 1992-04-28 |
| 4985825 | System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer | David A. Webb, Ricky C. Hetherington, Francis X. McKeen, Mark A. Firstenberg, John E. Murray +3 more | 1991-01-15 |
| 4888679 | Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements | Tryggve Fossum, Ricky C. Hetherington, Dwight P. Manley, Francis X. McKeen, John E. Murray | 1989-12-19 |