DH

Donald F. Hooper

IN Intel: 47 patents #694 of 30,777Top 3%
DE Digital Equipment: 16 patents #24 of 2,100Top 2%
Overall (All Time): #36,026 of 4,157,543Top 1%
63
Patents All Time

Issued Patents All Time

Showing 25 most recent of 63 patents

Patent #TitleCo-InventorsDate
8713569 Dynamic association and disassociation of threads to device functions based on requestor identification Peter Barry, Praveen Mosur 2014-04-29
7991983 Register set used in multithreaded parallel processor architecture Gilbert M. Wolrich, Matthew J. Adiletta, William R. Wheeler, Debra Bernstein 2011-08-02
7751402 Method and apparatus for gigabit packet assignment for multithreaded packet processing Gilbert M. Wolrich, Debra Bernstein, Matthew J. Adiletta 2010-07-06
7684970 Graphical user interface for use during processor simulation Eric Walker, Dennis Laurier Rivard, Mark Rosenbluth 2010-03-23
7546444 Register set used in multithreaded parallel processor architecture Gilbert M. Wolrich, Matthew J. Adiletta, William R. Wheeler, Debra Bernstein 2009-06-09
7515588 Method and apparatus to support a large internet protocol forwarding information base Uday Naik, Alok Kumar, Eswar Eduri 2009-04-07
7480706 Multi-threaded round-robin receive for fast network port Matthew J. Adiletta 2009-01-20
7477641 Providing access to data shared by packet processing threads Sanjeev Kumar Jain 2009-01-13
7471688 Scheduling system for transmission of cells to ATM virtual circuits and DSL ports Suresh Kalkunte 2008-12-30
7443836 Processing a data packet Mark Rosenbluth, Gilbert M. Wolrich, Matthew J. Adiletta, Hugh Wilkinson, Robert J. Kushlis 2008-10-28
7441245 Phasing for a multi-threaded network processor Mark Rosenbluth, Debra Bernstein, Michael F. Fallon, Sanjeev Kumar Jain, Gilbert M. Wolrich 2008-10-21
7433307 Flow control in a network environment Myles Wilde, Matthew J. Adiletta, Gilbert M. Wolrich 2008-10-07
7434221 Multi-threaded sequenced receive for fast network port stream of packets Matthew J. Adiletta, Gilbert M. Wolrich 2008-10-07
7421572 Branch instruction for processor with branching dependent on a specified bit in a register Gilbert M. Wolrich, Matthew J. Adiletta, William R. Wheeler, Debra Bernstein 2008-09-02
7391772 Network multicasting Suresh Kalkunte 2008-06-24
7352769 Multiple calendar schedule reservation structure and method Suresh Kalkunte 2008-04-01
7343563 Graphical user interface Richard Muratori, Myles Wilde 2008-03-11
7336606 Circular link list scheduling David Romano, Gilbert M. Wolrich 2008-02-26
7328429 Instruction operand tracing for software debug Eric Walker 2008-02-05
7289455 Network statistics Sanjeev Kumar Jain 2007-10-30
7248584 Network packet processing 2007-07-24
7240164 Folding for a multi-threaded network processor Hugh Wilkinson, Mark Rosenbluth, Debra Bernstein, Michael F. Fallon, Sanjeev Kumar Jain +2 more 2007-07-03
7206858 DSL transmit traffic shaper structure and procedure Serge Kornfeld, Robert P. Ottavi, John C. Cole 2007-04-17
7191321 Microengine for parallel processor architecture Debra Bernstein, Matthew J. Adiletta, Gilbert M. Wolrich, William R. Wheeler 2007-03-13
7191309 Double shift instruction for micro engine used in multithreaded parallel processor architecture Gilbert M. Wolrich, Matthew Adiletta, William R. Wheeler, Debra Bernstein 2007-03-13