| 12405843 |
Infrastructure processing unit |
Kshitij A. Doshi, Johan G. Van De Groenendaal, Edmund Chen, Ravi L. Sahita, Andrew J. Herdrich +3 more |
2025-09-02 |
|
| 12373335 |
Memory thin provisioning using memory pools |
Hugh Wilkinson, Douglas Carrigan, Bassam N. Coury, Matthew J. Adiletta, Durgesh Srivastava +3 more |
2025-07-29 |
|
| 11134021 |
Techniques for processor queue management |
Jonathan Kenny, Niall D. McDonnell, Andrew Cunningham, William Burroughs, Hugh Wilkinson |
2021-09-28 |
$36,743,000 |
| 10929323 |
Multi-core communication acceleration using hardware queue device |
Ren Wang, Yipeng Wang, Andrew J. Herdrich, Jr-Shian Tsai, Tsung-Yuan C. Tai +20 more |
2021-02-23 |
$31,062,000 |
| 10761979 |
Bit check processors, methods, systems, and instructions to check a bit with an indicated check bit value |
Hugh Wilkinson, William R. Wheeler |
2020-09-01 |
$24,773,000 |
| 10445271 |
Multi-core communication acceleration using hardware queue device |
Ren Wang, Namakkal N. Venkatesan, Edwin Verplanke, Stephen R. Van Doren, An Yan +20 more |
2019-10-15 |
$18,012,000 |
| 10216668 |
Technologies for a distributed hardware queue manager |
Ren Wang, Yipeng Wang, Jr-Shian Tsai, Andrew J. Herdrich, Tsung-Yuan C. Tai +17 more |
2019-02-26 |
$20,644,000 |
| 9830284 |
Memory mapping in a processor having multiple programmable units |
Gilbert M. Wolrich, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta |
2017-11-28 |
$12,678,000 |
| 9830285 |
Memory mapping in a processor having multiple programmable units |
Gilbert M. Wolrich, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta |
2017-11-28 |
$12,678,000 |
| 9824038 |
Memory mapping in a processor having multiple programmable units |
Gilbert M. Wolrich, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta |
2017-11-21 |
$11,290,000 |
| 9824037 |
Memory mapping in a processor having multiple programmable units |
Gilbert M. Wolrich, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta |
2017-11-21 |
$11,290,000 |
| 9535860 |
Arbitrating memory accesses via a shared memory fabric |
Daniel F. Cutter, Blaise Fanning, Ramadass Nagarajan, Jose Niell, Deepak Limaye +2 more |
2017-01-03 |
$8,191,000 |
| 9128818 |
Memory mapping in a processor having multiple programmable units |
Gilbert M. Wolrich, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta |
2015-09-08 |
$18,285,000 |
| 8738886 |
Memory mapping in a processor having multiple programmable units |
Gilbert M. Wolrich, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta |
2014-05-27 |
$13,313,000 |
| 8380923 |
Queue arrays in network devices |
Gilbert M. Wolrich, Mark Rosenbluth |
2013-02-19 |
$11,474,000 |
| 7991983 |
Register set used in multithreaded parallel processor architecture |
Gilbert M. Wolrich, Matthew J. Adiletta, William R. Wheeler, Donald F. Hooper |
2011-08-02 |
$15,238,000 |
| 7895239 |
Queue arrays in network devices |
Gilbert M. Wolrich, Mark Rosenbluth |
2011-02-22 |
$16,036,000 |
| RE41849 |
Parallel multi-threaded processing |
Gilbert M. Wolrich, Matthew J. Adiletta, William R. Wheeler |
2010-10-19 |
|
| 7751402 |
Method and apparatus for gigabit packet assignment for multithreaded packet processing |
Gilbert M. Wolrich, Matthew J. Adiletta, Donald F. Hooper |
2010-07-06 |
$9,424,000 |
| 7620702 |
Providing real-time control data for a network processor |
Gilbert M. Wolrich, Matthew J. Adiletta, William R. Wheeler |
2009-11-17 |
$26,173,000 |
| 7610451 |
Data transfer mechanism using unidirectional pull bus and push bus |
Gilbert M. Wolrich, Mark Rosenbluth, Matthew J. Adiletta |
2009-10-27 |
$28,062,000 |
| 7546444 |
Register set used in multithreaded parallel processor architecture |
Gilbert M. Wolrich, Matthew J. Adiletta, William R. Wheeler, Donald F. Hooper |
2009-06-09 |
$25,076,000 |
| 7487505 |
Multithreaded microprocessor with register allocation based on number of active threads |
Mark Rosenbluth, Gilbert M. Wolrich |
2009-02-03 |
$17,091,000 |
| 7467256 |
Processor having content addressable memory for block-based queue structures |
Sanjeev Kumar Jain, Gilbert M. Wolrich |
2008-12-16 |
$21,903,000 |
| 7441245 |
Phasing for a multi-threaded network processor |
Donald F. Hooper, Mark Rosenbluth, Michael F. Fallon, Sanjeev Kumar Jain, Gilbert M. Wolrich |
2008-10-21 |
$17,085,000 |
