Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
WB

William Burroughs — 34 Patents

Intel: 16 patents #2,596 of 30,777Top 9%
LSLsi: 10 patents #344 of 3,238Top 15%
ASAgere Systems: 3 patents #475 of 1,849Top 30%
UNUnisys: 3 patents #480 of 2,028Top 25%
ATAT&T: 1 patents #10,636 of 18,772Top 60%
Macungie, PA: #13 of 314 inventorsTop 5%
Pennsylvania: #1,494 of 74,527 inventorsTop 3%
Overall (All Time): #100,737 of 4,157,543Top 3%
34 Patents All Time
William Burroughs has been granted 34 US patents while listed as an inventor at Intel. The first was granted in 1988 and the most recent in July 2025. William Burroughs ranks #100,737 of 4,157,543 US inventors in our database (top 2.4%). Patent records list William Burroughs in Macungie, PA, US.

Issued Patents All Time

Showing 1–25 of 34 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12375408 Dynamic load balancing for multi-core computing environments Stephen T. Palermo, Bradley Chaddick, Gage Eads, Mrittika Ganguli, Abhishek Khade +6 more 2025-07-29
12309067 Hardware queue scheduling for multi-core computing environments Niall D. McDonnell, Gage Eads, Mrittika Ganguli, Chetan Hiremath, John Mangan +11 more 2025-05-20
12289239 Dynamic load balancing for multi-core computing environments Stephen T. Palermo, Bradley Chaddick, Gage Eads, Mrittika Ganguli, Abhishek Khade +6 more 2025-04-29
11709702 Work conserving, load balancing, and scheduling Joseph R. Hasting 2023-07-25 $28,608,000
11575607 Dynamic load balancing for multi-core computing environments Stephen T. Palermo, Bradley Chaddick, Gage Eads, Mrittika Ganguli, Abhishek Khade +6 more 2023-02-07 $11,877,000
11134021 Techniques for processor queue management Jonathan Kenny, Niall D. McDonnell, Andrew Cunningham, Debra Bernstein, Hugh Wilkinson 2021-09-28 $36,743,000
10929323 Multi-core communication acceleration using hardware queue device Ren Wang, Yipeng Wang, Andrew J. Herdrich, Jr-Shian Tsai, Tsung-Yuan C. Tai +20 more 2021-02-23 $31,062,000
10552205 Work conserving, load balancing, and scheduling Joseph R. Hasting 2020-02-04 $21,361,000
10445271 Multi-core communication acceleration using hardware queue device Ren Wang, Namakkal N. Venkatesan, Debra Bernstein, Edwin Verplanke, Stephen R. Van Doren +20 more 2019-10-15 $18,012,000
10437638 Method and apparatus for dynamically balancing task processing while maintaining task order Jerry Pirog, Joseph R. Hasting, Te K. Ma 2019-10-08 $19,521,000
10216668 Technologies for a distributed hardware queue manager Ren Wang, Yipeng Wang, Jr-Shian Tsai, Andrew J. Herdrich, Tsung-Yuan C. Tai +17 more 2019-02-26 $20,644,000
9864633 Network processor having multicasting protocol Deepak Mital, Joseph A. Manzella, Ritchie J. Peachey 2018-01-09 $14,051,000
9152564 Early cache eviction in a multi-flow network processor architecture Deepak Mital 2015-10-06 $14,030,000
9154442 Concurrent linked-list traversal for real-time hash processing in multi-core, multi-thread network processors Deepak Mital, Mohammad Reza Hakami 2015-10-06 $14,030,000
9094219 Network processor having multicasting protocol Deepak Mital, Joseph A. Manzella, Ritchie J. Peachey 2015-07-28 $15,934,000
9081742 Network communications processor architecture David P. Sonnier, Narender Vangati, Deepak Mital, Robert J. Munoz 2015-07-14 $20,297,000
8949838 Multi-threaded processing with hardware accelerators Deepak Mital, Eran Dosh, Eyal Rosin 2015-02-03
8910168 Task backpressure and deletion in a multi-flow network processor architecture Deepak Mital, Michael R. Betker 2014-12-09
8873550 Task queuing in a multi-flow network processor architecture Deepak Mital, Michael R. Betker, Joseph R. Hasting 2014-10-28
8868889 Instruction breakpoints in a multi-core, multi-thread network communications processor architecture Deepak Mital, Te K. Ma, Narender Vangati 2014-10-21
8677075 Memory manager for a network communications processor architecture Deepak Mital, David P. Sonnier, Steven J. Pollock, David A. Brown, Joseph R. Hasting 2014-03-18
8539199 Hash processing in a network communications processor architecture Deepak Mital, Mohammed Reza Hakami, Michael R. Betker 2013-09-17
8537832 Exception detection and thread rescheduling in a multi-core, multi-thread network processor Jerry Pirog, Deepak Mital 2013-09-17
8515965 Concurrent linked-list traversal for real-time hash processing in multi-core, multi-thread network processors Deepak Mital, Mohammed Reza Hakami 2013-08-20
8505013 Reducing data read latency in a network communications processor architecture Steven J. Pollock, Deepak Mital, Te K. Ma, Narender Vangati, Larry King 2013-08-06