Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10929323 | Multi-core communication acceleration using hardware queue device | Ren Wang, Yipeng Wang, Andrew J. Herdrich, Jr-Shian Tsai, Tsung-Yuan C. Tai +20 more | 2021-02-23 |
| 10445271 | Multi-core communication acceleration using hardware queue device | Ren Wang, Namakkal N. Venkatesan, Debra Bernstein, Edwin Verplanke, Stephen R. Van Doren +20 more | 2019-10-15 |
| 10437638 | Method and apparatus for dynamically balancing task processing while maintaining task order | William Burroughs, Joseph R. Hasting, Te K. Ma | 2019-10-08 |
| 10216668 | Technologies for a distributed hardware queue manager | Ren Wang, Yipeng Wang, Jr-Shian Tsai, Andrew J. Herdrich, Tsung-Yuan C. Tai +17 more | 2019-02-26 |
| 9444757 | Dynamic configuration of processing modules in a network communications processor architecture | Hakan I. Pekcan, Steven J. Pollock | 2016-09-13 |
| 8949582 | Changing a flow identifier of a packet in a multi-thread, multi-flow network processor | Deepak Mital, James Clee, Te K. Ma, Steven J. Pollock | 2015-02-03 |
| 8943507 | Packet assembly module for multi-core, multi-thread network processors | Deepak Mital, James Clee | 2015-01-27 |
| 8935483 | Concurrent, coherent cache access for multiple threads in a multi-core, multi-thread network processor | — | 2015-01-13 |
| 8910171 | Thread synchronization in a multi-thread network communications processor architecture | Deepak Mital, James Clee | 2014-12-09 |
| 8874878 | Thread synchronization in a multi-thread, multi-flow network communications processor architecture | Deepak Mital, James Clee | 2014-10-28 |
| 8537832 | Exception detection and thread rescheduling in a multi-core, multi-thread network processor | Deepak Mital, William Burroughs | 2013-09-17 |