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Modifying data streams without reordering in a multi-thread, multi-flow network processor |
Deepak Mital, James Clee |
2016-10-04 |
| 9444757 |
Dynamic configuration of processing modules in a network communications processor architecture |
Hakan I. Pekcan, Jerry Pirog |
2016-09-13 |
| 8949582 |
Changing a flow identifier of a packet in a multi-thread, multi-flow network processor |
Deepak Mital, James Clee, Jerry Pirog, Te K. Ma |
2015-02-03 |
| 8677075 |
Memory manager for a network communications processor architecture |
Deepak Mital, William Burroughs, David P. Sonnier, David A. Brown, Joseph R. Hasting |
2014-03-18 |
| 8505013 |
Reducing data read latency in a network communications processor architecture |
William Burroughs, Deepak Mital, Te K. Ma, Narender Vangati, Larry King |
2013-08-06 |
| 8489792 |
Transaction performance monitoring in a processor bus bridge |
Richard J. Byrne, David S. Masters, Michael R. Betker |
2013-07-16 |
| 8352669 |
Buffered crossbar switch system |
Ephrem C. Wu, Ting Zhou |
2013-01-08 |
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Inter-DSP signaling in a multiple DSP environment |
William Burroughs |
2008-06-17 |
| 7382170 |
Programmable delay circuit having reduced insertion delay |
— |
2008-06-03 |
| 6691190 |
Inter-DSP data exchange in a multiple DSP environment |
William Burroughs |
2004-02-10 |