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USPTO Patent Rankings Data through Dec 31, 2025
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Joseph R. Hasting — 9 Patents

Intel: 6 patents #6,200 of 30,777Top 25%
LSLsi: 3 patents #1,246 of 3,238Top 40%
Orefield, PA: #19 of 99 inventorsTop 20%
Pennsylvania: #9,298 of 74,527 inventorsTop 15%
Overall (All Time): #535,341 of 4,157,543Top 15%
9 Patents All Time
Joseph R. Hasting has been granted 9 US patents while listed as an inventor at Intel. The first was granted in 2013 and the most recent in July 2023. Joseph R. Hasting ranks #535,341 of 4,157,543 US inventors in our database (top 12.9%). Patent records list Joseph R. Hasting in Orefield, PA, US.

Issued Patents All Time

Showing 1–9 of 9 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11709702 Work conserving, load balancing, and scheduling William Burroughs 2023-07-25 $28,608,000
10929323 Multi-core communication acceleration using hardware queue device Ren Wang, Yipeng Wang, Andrew J. Herdrich, Jr-Shian Tsai, Tsung-Yuan C. Tai +20 more 2021-02-23 $31,062,000
10552205 Work conserving, load balancing, and scheduling William Burroughs 2020-02-04 $21,361,000
10445271 Multi-core communication acceleration using hardware queue device Ren Wang, Namakkal N. Venkatesan, Debra Bernstein, Edwin Verplanke, Stephen R. Van Doren +20 more 2019-10-15 $18,012,000
10437638 Method and apparatus for dynamically balancing task processing while maintaining task order William Burroughs, Jerry Pirog, Te K. Ma 2019-10-08 $19,521,000
10216668 Technologies for a distributed hardware queue manager Ren Wang, Yipeng Wang, Jr-Shian Tsai, Andrew J. Herdrich, Tsung-Yuan C. Tai +17 more 2019-02-26 $20,644,000
8873550 Task queuing in a multi-flow network processor architecture Deepak Mital, William Burroughs, Michael R. Betker 2014-10-28
8677075 Memory manager for a network communications processor architecture Deepak Mital, William Burroughs, David P. Sonnier, Steven J. Pollock, David A. Brown 2014-03-18
8499137 Memory manager for a network communications processor architecture Deepak Mital 2013-07-30