Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11580371 | Method and apparatus to efficiently process and execute Artificial Intelligence operations | — | 2023-02-14 |
| 9864633 | Network processor having multicasting protocol | Joseph A. Manzella, Ritchie J. Peachey, William Burroughs | 2018-01-09 |
| 9461930 | Modifying data streams without reordering in a multi-thread, multi-flow network processor | Steven J. Pollock, James Clee | 2016-10-04 |
| 9154442 | Concurrent linked-list traversal for real-time hash processing in multi-core, multi-thread network processors | Mohammad Reza Hakami, William Burroughs | 2015-10-06 |
| 9152564 | Early cache eviction in a multi-flow network processor architecture | William Burroughs | 2015-10-06 |
| 9094219 | Network processor having multicasting protocol | Joseph A. Manzella, Ritchie J. Peachey, William Burroughs | 2015-07-28 |
| 9081742 | Network communications processor architecture | David P. Sonnier, William Burroughs, Narender Vangati, Robert J. Munoz | 2015-07-14 |
| 8949838 | Multi-threaded processing with hardware accelerators | William Burroughs, Eran Dosh, Eyal Rosin | 2015-02-03 |
| 8949582 | Changing a flow identifier of a packet in a multi-thread, multi-flow network processor | James Clee, Jerry Pirog, Te K. Ma, Steven J. Pollock | 2015-02-03 |
| 8943507 | Packet assembly module for multi-core, multi-thread network processors | James Clee, Jerry Pirog | 2015-01-27 |
| 8910171 | Thread synchronization in a multi-thread network communications processor architecture | James Clee, Jerry Pirog | 2014-12-09 |
| 8910168 | Task backpressure and deletion in a multi-flow network processor architecture | William Burroughs, Michael R. Betker | 2014-12-09 |
| 8873550 | Task queuing in a multi-flow network processor architecture | William Burroughs, Michael R. Betker, Joseph R. Hasting | 2014-10-28 |
| 8874878 | Thread synchronization in a multi-thread, multi-flow network communications processor architecture | James Clee, Jerry Pirog | 2014-10-28 |
| 8868889 | Instruction breakpoints in a multi-core, multi-thread network communications processor architecture | Te K. Ma, Narender Vangati, William Burroughs | 2014-10-21 |
| 8761204 | Packet assembly module for multi-core, multi-thread network processors | James Clee, Robert J. Munoz | 2014-06-24 |
| 8677075 | Memory manager for a network communications processor architecture | William Burroughs, David P. Sonnier, Steven J. Pollock, David A. Brown, Joseph R. Hasting | 2014-03-18 |
| 8537832 | Exception detection and thread rescheduling in a multi-core, multi-thread network processor | Jerry Pirog, William Burroughs | 2013-09-17 |
| 8539199 | Hash processing in a network communications processor architecture | William Burroughs, Mohammed Reza Hakami, Michael R. Betker | 2013-09-17 |
| 8514874 | Thread synchronization in a multi-thread network communications processor architecture | James Clee | 2013-08-20 |
| 8515965 | Concurrent linked-list traversal for real-time hash processing in multi-core, multi-thread network processors | Mohammed Reza Hakami, William Burroughs | 2013-08-20 |
| 8505013 | Reducing data read latency in a network communications processor architecture | Steven J. Pollock, William Burroughs, Te K. Ma, Narender Vangati, Larry King | 2013-08-06 |
| 8499137 | Memory manager for a network communications processor architecture | Joseph R. Hasting | 2013-07-30 |
| 8407707 | Task queuing in a network communications processor architecture | David P. Sonnier, Balakrishnan Sundararaman, Shailendra Aulakh | 2013-03-26 |
| 8321385 | Hash processing in a network communications processor architecture | William Burroughs, Mohammed Reza Hakami | 2012-11-27 |