Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9864633 | Network processor having multicasting protocol | Deepak Mital, Ritchie J. Peachey, William Burroughs | 2018-01-09 |
| 9727508 | Address learning and aging for network bridging in a network processor | Robert J. Munoz, Zhong Guo, Walter A. Roper | 2017-08-08 |
| 9300597 | Statistics module for network processors in virtual local area networks | Michael T. Mangione, Nilesh S. Vora | 2016-03-29 |
| 9210082 | High speed network bridging | Zhong Guo | 2015-12-08 |
| 9094219 | Network processor having multicasting protocol | Deepak Mital, Ritchie J. Peachey, William Burroughs | 2015-07-28 |
| 8949578 | Sharing of internal pipeline resources of a network processor with external devices | Nilesh S. Vora, Walter A. Roper, Robert J. Munoz, David P. Sonnier | 2015-02-03 |
| 8705531 | Multicast address learning in an input/output adapter of a network processor | Nilesh S. Vora, Ritchie J. Peachey | 2014-04-22 |
| 8598910 | Timestamping logic with auto-adjust for varying system frequencies | John Leshchuk, Walter A. Roper | 2013-12-03 |
| 8488489 | Scalable packet-switch | — | 2013-07-16 |
| 6810024 | Auto-detection system and method for a network transceiver | Jack Lee, Robert H. Leonowich, Matthew Tota | 2004-10-26 |
| 6700898 | Multiplexed output of status signals in ethernet transceiver | Edmond H. Barakat | 2004-03-02 |
| 5517147 | Multiple-phase clock signal generator for integrated circuits, comprising PLL, counter, and logic circuits | William Burroughs, Andrew Neely | 1996-05-14 |