| 9830284 |
Memory mapping in a processor having multiple programmable units |
Gilbert M. Wolrich, Debra Bernstein, Christopher Dolan, Matthew J. Adiletta |
2017-11-28 |
$12,678,000 |
| 9830285 |
Memory mapping in a processor having multiple programmable units |
Gilbert M. Wolrich, Debra Bernstein, Christopher Dolan, Matthew J. Adiletta |
2017-11-28 |
$12,678,000 |
| 9824037 |
Memory mapping in a processor having multiple programmable units |
Gilbert M. Wolrich, Debra Bernstein, Christopher Dolan, Matthew J. Adiletta |
2017-11-21 |
$11,290,000 |
| 9824038 |
Memory mapping in a processor having multiple programmable units |
Gilbert M. Wolrich, Debra Bernstein, Christopher Dolan, Matthew J. Adiletta |
2017-11-21 |
$11,290,000 |
| 9128818 |
Memory mapping in a processor having multiple programmable units |
Gilbert M. Wolrich, Debra Bernstein, Christopher Dolan, Matthew J. Adiletta |
2015-09-08 |
$18,285,000 |
| 8738886 |
Memory mapping in a processor having multiple programmable units |
Gilbert M. Wolrich, Debra Bernstein, Christopher Dolan, Matthew J. Adiletta |
2014-05-27 |
$13,313,000 |
| 8073892 |
Cryptographic system, method and multiplier |
Wajdi K. Feghali, William C. Hasenplaugh, Gilbert M. Wolrich, Vinodh Gopal, Gunnar Gaubatz |
2011-12-06 |
$25,306,000 |
| 8020142 |
Hardware accelerator |
Gilbert M. Wolrich, William C. Hasenplaugh, Wajdi K. Feghali, Vinodh Gopal, Gunnar Gaubatz |
2011-09-13 |
$15,671,000 |
| 7725624 |
System and method for cryptography processing units and multiplier |
Wajdi K. Feghali, William C. Hasenplaugh, Gilbert M. Wolrich, Vinodh Gopal, Gunnar Gaubatz |
2010-05-25 |
$11,401,000 |
| 7305500 |
Sram controller for parallel processor architecture including a read queue and an order queue for handling requests |
Matthew J. Adiletta, William R. Wheeler, James Redfield, Gilbert M. Wolrich |
2007-12-04 |
$21,616,000 |
| 6728845 |
SRAM controller for parallel processor architecture and method for controlling access to a RAM using read and read/write queues |
Matthew J. Adiletta, William R. Wheeler, James Redfield, Gilbert M. Wolrich |
2004-04-27 |
$48,199,000 |
| 6694380 |
Mapping requests from a processing unit that uses memory-mapped input-output space |
Gilbert M. Wolrich, Debra Bernstein, Christopher Dolan, Matthew J. Adiletta |
2004-02-17 |
$33,660,000 |
| 6681300 |
Read lock miss control and queue management |
Gilbert M. Wolrich, William R. Wheeler, Matthew J. Adiletta, Debra Bernstein |
2004-01-20 |
$75,155,000 |
| 6671827 |
Journaling for parallel hardware threads in multithreaded processor |
James D. Guilford, William R. Wheeler, Matthew J. Adiletta |
2003-12-30 |
$55,813,000 |
| 6631462 |
Memory shared between processing threads |
Gilbert M. Wolrich, Matthew J. Adiletta, William R. Wheeler, Debra Bernstein |
2003-10-07 |
$52,834,000 |
| 6427196 |
SRAM controller for parallel processor architecture including address and command queue and arbiter |
Matthew J. Adiletta, William R. Wheeler, James Redfield, Gilbert M. Wolrich |
2002-07-30 |
$108,056,000 |
| 6324624 |
Read lock miss control and queue management |
Gilbert M. Wolrich, William R. Wheeler, Matthew J. Adiletta, Debra Bernstein |
2001-11-27 |
$206,664,000 |
