Issued Patents All Time
Showing 25 most recent of 79 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12373335 | Memory thin provisioning using memory pools | Debra Bernstein, Hugh Wilkinson, Douglas Carrigan, Bassam N. Coury, Matthew J. Adiletta +3 more | 2025-07-29 |
| 11237840 | All in one mobile computing device | Matthew J. Adiletta, Myles Wilde, Michael F. Fallon, Amit Y. Kumar, Chengda Yang +1 more | 2022-02-01 |
| 10922148 | Integrated android and windows device | Matthew J. Adiletta, Myles Wilde, Michael F. Fallon, Aaron Gorius, Amit Y. Kumar +1 more | 2021-02-16 |
| 10761979 | Bit check processors, methods, systems, and instructions to check a bit with an indicated check bit value | Hugh Wilkinson, Debra Bernstein | 2020-09-01 |
| 10032431 | Mobile computing device technology and systems and methods utilizing the same | Myles Wilde, Matthew J. Adiletta, Michael F. Fallon, Thomas M. Garrison, Aaron Gorius +1 more | 2018-07-24 |
| 8667110 | Method and apparatus for providing a remotely managed expandable computer system | Johan van de Groenendaal, Matthew J. Adiletta, Myles Wilde, Michael F. Fallon, Aaron Gorius +3 more | 2014-03-04 |
| 8316191 | Memory controllers for processor having multiple programmable units | Bradley A. Burres, Matthew J. Adiletta, Gilbert M. Wolrich | 2012-11-20 |
| 7991983 | Register set used in multithreaded parallel processor architecture | Gilbert M. Wolrich, Matthew J. Adiletta, Debra Bernstein, Donald F. Hooper | 2011-08-02 |
| 7911811 | Switching power supply with increased efficiency at light load | Wei-Liang Lin | 2011-03-22 |
| RE41849 | Parallel multi-threaded processing | Gilbert M. Wolrich, Debra Bernstein, Matthew J. Adiletta | 2010-10-19 |
| 7743235 | Processor having a dedicated hash unit integrated within | Gilbert M. Wolrich, Matthew J. Adiletta | 2010-06-22 |
| 7681018 | Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set | Gilbert M. Wolrich, Matthew J. Adiletta | 2010-03-16 |
| 7620702 | Providing real-time control data for a network processor | Gilbert M. Wolrich, Debra Bernstein, Matthew J. Adiletta | 2009-11-17 |
| 7546444 | Register set used in multithreaded parallel processor architecture | Gilbert M. Wolrich, Matthew J. Adiletta, Debra Bernstein, Donald F. Hooper | 2009-06-09 |
| 7532318 | Wafer edge inspection | Steven W. Meeks, Rusmin Kudinar, Hung Phi Nguyen, Vamsi Velidandla, Anoop Somanchi +1 more | 2009-05-12 |
| 7424579 | Memory controller for processor having multiple multithreaded programmable units | Bradley A. Burres, Matthew J. Adiletta, Gilbert M. Wolrich | 2008-09-09 |
| 7421572 | Branch instruction for processor with branching dependent on a specified bit in a register | Gilbert M. Wolrich, Matthew J. Adiletta, Debra Bernstein, Donald F. Hooper | 2008-09-02 |
| 7305500 | Sram controller for parallel processor architecture including a read queue and an order queue for handling requests | Matthew J. Adiletta, James Redfield, Daniel Cutter, Gilbert M. Wolrich | 2007-12-04 |
| 7278301 | System for sensing a sample | Thomas H. McWaid, Peter G. Panagas, Steven Eaton, Amin Samsavar | 2007-10-09 |
| 7197724 | Modeling a logic design | Timothy Fennell | 2007-03-27 |
| 7191321 | Microengine for parallel processor architecture | Debra Bernstein, Donald F. Hooper, Matthew J. Adiletta, Gilbert M. Wolrich | 2007-03-13 |
| 7191309 | Double shift instruction for micro engine used in multithreaded parallel processor architecture | Gilbert M. Wolrich, Matthew Adiletta, Debra Bernstein, Donald F. Hooper | 2007-03-13 |
| 7161667 | Wafer edge inspection | Steven W. Meeks, Rusmin Kudinar, Hung Phi Nguyen | 2007-01-09 |
| 7161668 | Wafer edge inspection | Steven W. Meeks, Rusmin Kudinar, Hung Phi Nguyen | 2007-01-09 |
| 7130784 | Logic simulation | Timothy Fennell, Matthew J. Adiletta | 2006-10-31 |