Issued Patents All Time
Showing 26–50 of 79 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7111296 | Thread signaling in multi-threaded processor | Gilbert M. Wolrich, Debra Bernstein, Donald F. Hooper, Matthew J. Adiletta | 2006-09-19 |
| 7107201 | Simulating a logic design | Matthew J. Adiletta | 2006-09-12 |
| 7100430 | Dual stage instrument for scanning a specimen | Amin Samsavar, Steven Eaton, Jian-Ping Zhuang | 2006-09-05 |
| 7093224 | Model-based logic design | Matthew J. Adiletta, Christopher Aaron Clark, Timothy J. Fennel | 2006-08-15 |
| 7073156 | Gate estimation process and method | Matthew J. Adiletta | 2006-07-04 |
| 7016826 | Apparatus and method of developing software for a multi-processor chip | Lai-Wah Hui, Donald F. Hooper, Serge Kornfeld, James D. Guilford | 2006-03-21 |
| 7006698 | Method and apparatus for compressing a video image | Matthew J. Adiletta, King-Wai Chow, Samuel Ho, Robert C. Rose, Subramania Sudharsanan | 2006-02-28 |
| 6983350 | SDRAM controller for parallel processor architecture | Bradley A. Burres, Matthew J. Adiletta, Gilbert M. Wolrich | 2006-01-03 |
| 6983427 | Generating a logic design | Matthew J. Adiletta | 2006-01-03 |
| 6931917 | System for sensing a sample | Thomas H. McWaid, Peter G. Panagas, Steven Eaton, Amin Samsavar | 2005-08-23 |
| 6859913 | Representing a simulation model using a hardware configuration database | Timothy Fennell | 2005-02-22 |
| 6823438 | Method for memory allocation and management using push/pop apparatus | Donald F. Hooper, Gilbert M. Wolrich, Matthew J. Adiletta | 2004-11-23 |
| 6760478 | Method and apparatus for performing two pass quality video compression through pipelining and buffer management | Matthew J. Adiletta, King-Wai Chow, Samuel Ho, Robert C. Rose, Duane E. Galbi | 2004-07-06 |
| 6728845 | SRAM controller for parallel processor architecture and method for controlling access to a RAM using read and read/write queues | Matthew J. Adiletta, James Redfield, Daniel Cutter, Gilbert M. Wolrich | 2004-04-27 |
| 6721925 | Employing intelligent logical models to enable concise logic representations for clarity of design description and for rapid design capture | Timothy Fennell, Matthew J. Adiletta | 2004-04-13 |
| 6708321 | Generating a function within a logic design using a dialog box | Mathew J. Adiletta, Timothy Fennell | 2004-03-16 |
| 6681300 | Read lock miss control and queue management | Gilbert M. Wolrich, Daniel Cutter, Matthew J. Adiletta, Debra Bernstein | 2004-01-20 |
| 6671827 | Journaling for parallel hardware threads in multithreaded processor | James D. Guilford, Matthew J. Adiletta, Daniel Cutter | 2003-12-30 |
| 6668311 | Method for memory allocation and management using push/pop apparatus | Donald F. Hooper, Gilbert M. Wolrich, Matthew J. Adiletta | 2003-12-23 |
| 6668317 | Microengine for parallel processor architecture | Debra Bernstein, Donald F. Hooper, Matthew J. Adiletta, Gilbert M. Wolrich | 2003-12-23 |
| 6643836 | Displaying information relating to a logic design | Matthew J. Adiletta | 2003-11-04 |
| 6640329 | Real-time connection error checking method and process | Matthew J. Adiletta | 2003-10-28 |
| 6631462 | Memory shared between processing threads | Gilbert M. Wolrich, Matthew J. Adiletta, Daniel Cutter, Debra Bernstein | 2003-10-07 |
| 6629237 | Solving parallel problems employing hardware multi-threading in a parallel processing environment | Gilbert M. Wolrich, Matthew J. Adiletta | 2003-09-30 |
| 6625654 | Thread signaling in multi-threaded network processor | Gilbert M. Wolrich, Debra Bernstein, Donald F. Hooper, Matthew J. Adiletta | 2003-09-23 |