Issued Patents All Time
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11068264 | Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers | Chris J. Newburn, Simon C. Steely, Jr., Samantika S. Sury | 2021-07-20 |
| 10402168 | Low energy consumption mantissa multiplication for floating point multiply-add operations | Kermin Fleming, Tryggve Fossum, Simon C. Steely, Jr. | 2019-09-03 |
| 10379855 | Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers | Chris J. Newburn, Simon C. Steely, Jr., Samantika S. Sury | 2019-08-13 |
| 10102124 | High bandwidth full-block write commands | Simon C. Steely, Jr., Joel S. Emer, Samantika Subramaniam | 2018-10-16 |
| 9934146 | Hardware apparatuses and methods to control cache line coherency | Simon C. Steely, Jr., Samantika S. Sury | 2018-04-03 |
| 9740617 | Hardware apparatuses and methods to control cache line coherence | Samantika S. Sury, Simon C. Steely, Jr., Joel S. Emer, David A. Webb | 2017-08-22 |
| 9734069 | Multicast tree-based data distribution in distributed shared cache | Simon C. Steely, Jr., Samantika S. Sury | 2017-08-15 |
| 9727482 | Address range priority mechanism | Simon C. Steely, Jr., Samantika S. Sury | 2017-08-08 |
| 9588889 | Domain state | Simon C. Steely, Jr., Joel S. Emer | 2017-03-07 |
| 9477610 | Address range priority mechanism | Simon C. Steely, Jr., Samantika Subramaniam | 2016-10-25 |
| 9418016 | Method and apparatus for optimizing the usage of cache memories | Simon C. Steely, Jr., Joel S. Emer | 2016-08-16 |
| 9317263 | Hardware compilation and/or translation with fault detection and roll back functionality | Nicholas Cheng Hwa Chee, Tryggve Fossum | 2016-04-19 |
| 9294419 | Scalable multi-layer 2D-mesh routers | Tryggve Fossum, Judson S. Leonard | 2016-03-22 |
| 9262327 | Signature based hit-predicting cache | Simon C. Steely, Jr., Aamer Jaleel, Joel S. Emer, Carole-Jean Wu | 2016-02-16 |
| 9250682 | Distributed power management for multi-core processors | Tryggve Fossum | 2016-02-02 |
| 9251073 | Update mask for handling interaction between fills and updates | Simon C. Steely, Jr. | 2016-02-02 |
| 9201792 | Short circuit of probes in a chain | Simon C. Steely, Jr., Samantika Subramaniam, Joel S. Emer | 2015-12-01 |
| 9146871 | Retrieval of previously accessed data in a multi-core processor | Simon C. Steely, Jr., Joel S. Emer | 2015-09-29 |
| 9104474 | Variable precision floating point multiply-add circuit | Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Ram Krishnamurthy, Randy L. Allmon +1 more | 2015-08-11 |
| 9037804 | Efficient support of sparse data structure access | Simon C. Steely, Jr., Joel S. Emer | 2015-05-19 |
| 8893094 | Hardware compilation and/or translation with fault detection and roll back functionality | Nicholas Cheng Hwa Chee, Tryggve Fossum | 2014-11-18 |
| 8769201 | Technique for controlling computing resources | Joel S. Emer, Tryggve Fossum, Aamer Jaleel, Simon C. Steely, Jr. | 2014-07-01 |
| 8438335 | Probe speculative address file | Simon C. Steely, Jr. | 2013-05-07 |
| 8407421 | Cache spill management techniques using cache spill prediction | Simon C. Steely, Jr., Aamer Jaleel, George Z. Chrysos | 2013-03-26 |
| 8229109 | Modular reduction using folding | Gunnar Gaubatz, Vinodh Gopal | 2012-07-24 |