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Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
AJ

Aamer Jaleel — 24 Patents

Intel: 21 patents #1,927 of 30,777Top 7%
NVIDIA: 3 patents #2,179 of 7,811Top 30%
Northborough, MA: #33 of 343 inventorsTop 10%
Massachusetts: #4,431 of 88,656 inventorsTop 5%
Overall (All Time): #168,038 of 4,157,543Top 5%
24 Patents All Time
Aamer Jaleel has been granted 24 US patents while listed as an inventor at Intel. The first was granted in 2010 and the most recent in June 2025. Aamer Jaleel ranks #168,038 of 4,157,543 US inventors in our database (top 4.0%). Patent records list Aamer Jaleel in Northborough, MA, US.

Patents per Year

Patents granted per year, 2010 to 2025Bar chart with a peak of 3 patents in 2013.peak 32010: 1 patents20102012: 1 patents2013: 3 patents20132014: 3 patents2016: 3 patents20162017: 3 patents2018: 1 patents20182019: 3 patents2020: 2 patents20202022: 1 patents2023: 1 patents20232024: 1 patents2025: 1 patents2025

Issued Patents All Time

Showing 1–24 of 24 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12321230 Alias-free tagged error correcting codes for machine memory operations Michael Sullivan, Mohamed Tarek Bnziad Mohamed Hassan 2025-06-03
12135781 Implementing hardware-based memory safety for a graphic processing unit Mohamed Tarek Bnziad Mohamed Hassan, Mark Stephenson 2024-11-05 $9,642,537,000
11836361 Implementing compiler-based memory safety for a graphic processing unit Mohamed Tarek Bnziad Mohamed Hassan, Mark Stephenson, Michael Sullivan 2023-12-05 $1,234,193,000
11513957 Processor and method implementing a cacheline demote machine instruction Ren Wang, Andrew J. Herdrich, Yen-Cheng Liu, Herbert Hum, Jong Soo Park +10 more 2022-11-29 $14,086,000
10853276 Executing distributed memory operations using processing elements connected by distributed channels Bushra Ahsan, Michael C. Adler, Neal C. Crago, Joel S. Emer, Angshuman Parashar +1 more 2020-12-01 $25,476,000
10817425 Hardware/software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads Ren Wang, Andrew J. Herdrich, Yen-Cheng Liu, Herbert Hum, Jong Soo Park +10 more 2020-10-27 $34,955,000
10387319 Processors, methods, and systems for a configurable spatial accelerator with memory system performance, power reduction, and atomics support features Michael C. Adler, Chiachen Chou, Neal C. Crago, Kermin Fleming, Kent D. Glossop +3 more 2019-08-20 $17,708,000
10331583 Executing distributed memory operations using processing elements connected by distributed channels Bushra Ahsan, Michael C. Adler, Neal C. Crago, Joel S. Emer, Angshuman Parashar +1 more 2019-06-25 $17,766,000
10284470 Technologies for network device flow lookup management Ren Wang, Namakkal N. Venkatesan, Tsung-Yuan C. Tai, Sameh Gobriel, Christian Maciocco 2019-05-07 $24,403,000
10102134 Instruction and logic for run-time evaluation of multiple prefetchers Zeshan A. Chishti, Christopher B. Wilkerson, Seth H. Pugsley, Peng-Fei Chuang, Robert L. Scott +2 more 2018-10-16 $21,459,000
9792212 Virtual shared cache mechanism in a processing device Yen-Cheng Liu, Bongjin Jung, Zeshan A. Chishti, Adrian C. Moga, Eric Delano +1 more 2017-10-17 $9,876,000
9720730 Providing an asymmetric multicore processor system transparently to an operating system Boris Ginzburg, Ilya Osadchiy, Ronny Ronen, Eliezer Weissmann, Michael Mishaeli +13 more 2017-08-01 $11,137,000
9710380 Managing shared cache by multi-core processor Ren Wang, Kevin B. Theobald, Zeshan A. Chishti, Zhaojuan Bian, Tsung-Yuan C. Tai 2017-07-18 $6,909,000
9378021 Instruction and logic for run-time evaluation of multiple prefetchers Zeshan A. Chishti, Christopher B. Wilkerson, Seth H. Pugsley, Peng-Fei Chuang, Robert L. Scott +2 more 2016-06-28 $11,945,000
9286128 Processor scheduling with thread performance estimation on cores of different types Kenzo Van Craeynest, Paolo Narvaez, Joel S. Emer 2016-03-15 $12,478,000
9262327 Signature based hit-predicting cache Simon C. Steely, Jr., William C. Hasenplaugh, Joel S. Emer, Carole-Jean Wu 2016-02-16 $10,295,000
8839259 Thread scheduling on multiprocessor systems Wenlong Li, Tao Wang, Yimin Zhang 2014-09-16 $19,366,000
8769209 Method and apparatus for achieving non-inclusive cache performance with inclusive caches Simon C. Steely, Jr., Eric R. Borch, Malini K. Bhandaru, Joel S. Emer 2014-07-01 $13,029,000
8769201 Technique for controlling computing resources William C. Hasenplaugh, Joel S. Emer, Tryggve Fossum, Simon C. Steely, Jr. 2014-07-01 $13,029,000
8533422 Instruction prefetching using cache line history Samantika Subramaniam, Simon C. Steely, Jr. 2013-09-10 $11,653,000
8407421 Cache spill management techniques using cache spill prediction Simon C. Steely, Jr., William C. Hasenplaugh, George Z. Chrysos 2013-03-26 $14,049,000
8347301 Device, system, and method of scheduling tasks of a multithreaded application Wenlong Li, Xiaofeng Tong 2013-01-01
8132172 Thread scheduling on multiprocessor systems Wenlong Li, Tao Wang, Yimin Zhang 2012-03-06 $22,588,000
7725657 Dynamic quality of service (QoS) for a shared cache William C. Hasenplaugh, Li Zhao, Ravishankar Iyer, Ramesh Illikkal, Srihari Makineni +2 more 2010-05-25 $11,401,000