Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417182 | De-prioritizing speculative code lines in on-chip caches | Anant Vithal Nori, Prathmesh Kallurkar, Niranjan Soundararajan, Sreenivas Subramoney, Lihu Rappoport +2 more | 2025-09-16 |
| 12327045 | System, apparatus, and method for scheduling metadata requests | Ramya Jayaram Masti, Thomas Toll, Vincent Edward Von Bokern | 2025-06-10 |
| 12271306 | Integrated three-dimensional (3D) DRAM cache | Wilfred Gomes, Abhishek A. Sharma | 2025-04-08 |
| 11513957 | Processor and method implementing a cacheline demote machine instruction | Ren Wang, Andrew J. Herdrich, Yen-Cheng Liu, Herbert Hum, Jong Soo Park +10 more | 2022-11-29 |
| 10817425 | Hardware/software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads | Ren Wang, Andrew J. Herdrich, Yen-Cheng Liu, Herbert Hum, Jong Soo Park +10 more | 2020-10-27 |
| 10725919 | Processors having virtually clustered cores and cache slices | Herbert Hum, Brinda Ganesh, James Vash, Ganesh Kumar, Leena K. Puthiyedath +6 more | 2020-07-28 |
| 10725920 | Processors having virtually clustered cores and cache slices | Herbert Hum, Brinda Ganesh, James Vash, Ganesh Kumar, Leena K. Puthiyedath +6 more | 2020-07-28 |
| 10705960 | Processors having virtually clustered cores and cache slices | Herbert Hum, Brinda Ganesh, James Vash, Ganesh Kumar, Leena K. Puthiyedath +6 more | 2020-07-07 |
| 10073779 | Processors having virtually clustered cores and cache slices | Herbert Hum, Brinda Ganesh, James Vash, Ganesh Kumar, Leena K. Puthiyedath +6 more | 2018-09-11 |
| 9792212 | Virtual shared cache mechanism in a processing device | Yen-Cheng Liu, Aamer Jaleel, Bongjin Jung, Zeshan A. Chishti, Eric Delano +1 more | 2017-10-17 |
| 9436605 | Cache coherency apparatus and method minimizing memory writeback operations | Jeffrey D. Chamberlain, Vedaraman Geetha, Robert G. Blankenship, Yen-Cheng Liu, Herbert Hum +1 more | 2016-09-06 |
| 9418009 | Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory | Vedaraman Geetha, Bahaa Fahim, Robert G. Blankenship, Yen-Cheng Liu, Jeffrey D. Chamberlain +1 more | 2016-08-16 |
| 9081688 | Obtaining data for redundant multithreading (RMT) execution | Glenn J. Hinton, Steven Raasch, Sebastien Hily, John G. Holm, Ronak Singhal +4 more | 2015-07-14 |
| 9015415 | Multi-processor computing system having fast processor response to cache agent request capacity limit warning | Ankush Varma, Liqun Cheng | 2015-04-21 |
| 8838935 | Apparatus, method, and system for implementing micro page tables | Glenn Hinton, Madhavan Parthasarathy, Rajesh S. Parthasarathy, Muthukumar P. Swaminathan, Raj K. Ramanujan +5 more | 2014-09-16 |
| 8631210 | Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines | Malcolm Mandviwalla, Vedaraman Geetha, Herbert Hum | 2014-01-14 |
| 8392665 | Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines | Malcolm Mandviwalla, Vedaraman Geetha, Herbert Hum | 2013-03-05 |
| 8041898 | Method, system and apparatus for reducing memory traffic in a distributed memory system | Rajat Agarwal, Malcolm Mandviwalla | 2011-10-18 |
| 7552247 | Increased computer peripheral throughput by using data available withholding | Thomas B. Berg, Dale Beyer | 2009-06-23 |
| 6848026 | Caching memory contents into cache partitions based on memory locations | Donald R. DeSota, Carl E. Love, Russell M. Clapp | 2005-01-25 |
| 6807586 | Increased computer peripheral throughput by using data available withholding | Thomas B. Berg, Dale Beyer | 2004-10-19 |