RS

Ronak Singhal

IN Intel: 38 patents #927 of 30,777Top 4%
Overall (All Time): #83,853 of 4,157,543Top 3%
38
Patents All Time

Issued Patents All Time

Showing 25 most recent of 38 patents

Patent #TitleCo-InventorsDate
12417182 De-prioritizing speculative code lines in on-chip caches Anant Vithal Nori, Prathmesh Kallurkar, Niranjan Soundararajan, Sreenivas Subramoney, Lihu Rappoport +2 more 2025-09-16
12198186 Systems, apparatuses, and methods for resource bandwidth enforcement Andrew J. Herdrich, Edwin Verplanke, Ravishankar Iyer, Christopher C. Gianos, Jeffrey D. Chamberlain +2 more 2025-01-14
12130740 Apparatuses and methods for a processor architecture Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther +9 more 2024-10-29
12039336 Packed data element predication processors, methods, systems, and instructions Bret L. Toll, Buford M. Guy, Mishali Naik 2024-07-16
11442734 Packed data element predication processors, methods, systems, and instructions Bret L. Toll, Buford M. Guy, Mishali Naik 2022-09-13
11294809 Apparatuses and methods for a processor architecture Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther +9 more 2022-04-05
11048588 Monitoring the operation of a processor Gilbert Neiger, Andrew V. Anderson, Richard Uhlig, David M. Durham, Xiangbin Wu +1 more 2021-06-29
10963257 Packed data element predication processors, methods, systems, and instructions Bret L. Toll, Buford M. Guy, Mishali Naik 2021-03-30
10719355 Criticality based port scheduling Pooja Roy, Jayesh Gaur, Sreenivas Subramoney, Zeev Sperber, Alexandr Titov +5 more 2020-07-21
10599547 Monitoring the operation of a processor Gilbert Neiger, Andrew V. Anderson, Richard Uhlig, David M. Durham, Xiangbin Wu +1 more 2020-03-24
10579414 Misprediction-triggered local history-based branch prediction Niranjan Soundararajan, Saurabh Gupta, Sreenivas Subramoney, Rahul Pal, Ragavendra Natarajan +3 more 2020-03-03
10496413 Efficient hardware-based extraction of program instructions for critical paths Jayesh Gaur, Pooja Roy, Sreenivas Subramoney, Hong Wang 2019-12-03
10430193 Packed data element predication processors, methods, systems, and instructions Bret L. Toll, Buford M. Guy, Mishali Naik 2019-10-01
10228941 Processors, methods, and systems to access a set of registers as either a plurality of smaller registers or a combined larger register Bret L. Toll, Buford M. Guy, Mishali Naik 2019-03-12
10170165 Multiple register memory access instructions, processors, methods, and systems Glenn J. Hinton, Bret L. Toll 2019-01-01
10163468 Multiple register memory access instructions, processors, methods, and systems Glenn J. Hinton, Bret L. Toll 2018-12-25
10153011 Multiple register memory access instructions, processors, methods, and systems Glenn J. Hinton, Bret L. Toll 2018-12-11
10153012 Multiple register memory access instructions, processors, methods, and systems Glenn J. Hinton, Bret L. Toll 2018-12-11
10141033 Multiple register memory access instructions, processors, methods, and systems Glenn J. Hinton, Bret L. Toll 2018-11-27
10102888 Multiple register memory access instructions, processors, methods, and systems Glenn J. Hinton, Bret L. Toll 2018-10-16
10089229 Cache allocation with code and data prioritization Andrew J. Herdrich, Edwin Verplanke, Ravishankar Iyer, Christopher C. Gianos, Jeffrey D. Chamberlain +2 more 2018-10-02
9990202 Packed data element predication processors, methods, systems, and instructions Bret L. Toll, Buford M. Guy, Mishali Naik 2018-06-05
9858167 Monitoring the operation of a processor Gilbert Neiger, Andrew V. Anderson, Richard Uhlig, David M. Durham, Xiangbin Wu +1 more 2018-01-02
9786338 Multiple register memory access instructions, processors, methods, and systems Glenn J. Hinton, Bret L. Toll 2017-10-10
9594648 Controlling non-redundant execution in a redundant multithreading (RMT) processor Glenn J. Hinton, Steven Raasch, Sebastien Hily, John G. Holm, Avinash Sodani +1 more 2017-03-14