Issued Patents All Time
Showing 25 most recent of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430135 | Device, method, and system to facilitate improved bandwidth of a branch prediction unit | Sumeet Bandishte, Jayesh Gaur, Franck Sala, Alexey Y. Sivtsov, Jared W. Stark, IV +1 more | 2025-09-30 |
| 12423075 | Code prefetch instruction | Ahmad Yasin, Jared W. Stark, IV, Jeffrey Baxter, Israel Diamand, Pavel Fridman +2 more | 2025-09-23 |
| 12417182 | De-prioritizing speculative code lines in on-chip caches | Anant Vithal Nori, Prathmesh Kallurkar, Niranjan Soundararajan, Sreenivas Subramoney, Hanna Alam +2 more | 2025-09-16 |
| 12236243 | Apparatuses and methods for speculative execution side channel mitigation | Jason W. Brandt, Deepak Gupta, Rodrigo Branco, Joseph Nuzman, Robert S. Chappell +11 more | 2025-02-25 |
| 12130740 | Apparatuses and methods for a processor architecture | Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther +9 more | 2024-10-29 |
| 11656971 | Technology for dynamically tuning processor features | Adarsh Chauhan, Jayesh Gaur, Franck Sala, Zeev Sperber, Adi Yoaz +1 more | 2023-05-23 |
| 11645078 | Detecting a dynamic control flow re-convergence point for conditional branches in hardware | Adarsh Chauhan, Franck Sala, Jayesh Gaur, Zeev Sperber, Adi Yoaz +1 more | 2023-05-09 |
| 11635965 | Apparatuses and methods for speculative execution side channel mitigation | Jason W. Brandt, Deepak Gupta, Rodrigo Branco, Joseph Nuzman, Robert S. Chappell +11 more | 2023-04-25 |
| 11294809 | Apparatuses and methods for a processor architecture | Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther +9 more | 2022-04-05 |
| 11256599 | Technology for dynamically tuning processor features | Adarsh Chauhan, Jayesh Gaur, Franck Sala, Zeev Sperber, Adi Yoaz +1 more | 2022-02-22 |
| 11150979 | Accelerating memory fault resolution by performing fast re-fetching | Zeev Sperber, Stanislav Shwartsman, Jared W. Stark, IV, Igor Yanover, George Leifman | 2021-10-19 |
| 11086627 | Instruction length decoder system and method | Nir Tell, Shahar Sandor, Amotz Yagev, Michael Hermony, Sagie Goldenberg | 2021-08-10 |
| 10949208 | System, apparatus and method for context-based override of history-based branch predictions | Saurabh Gupta, Niranjan Soundararajan, Ragavendra Natarajan, Jared W. Stark, IV, Sreenivas Subramoney | 2021-03-16 |
| 10915421 | Technology for dynamically tuning processor features | Adarsh Chauhan, Jayesh Gaur, Franck Sala, Zeev Sperber, Adi Yoaz +1 more | 2021-02-09 |
| 10754655 | Automatic predication of hard-to-predict convergent branches | Adarsh Chauhan, Hong Wang, Jayesh Gaur, Zeev Sperber, Sumeet Bandishte +4 more | 2020-08-25 |
| 10719355 | Criticality based port scheduling | Pooja Roy, Jayesh Gaur, Sreenivas Subramoney, Zeev Sperber, Alexandr Titov +5 more | 2020-07-21 |
| 10649783 | Multicore system for fusing instructions queued during a dynamically adjustable time window | Ido Ouziel, Robert Valentine, Ron Gabor, Pankaj Raghuvanshi | 2020-05-12 |
| 10579535 | Defragmented and efficient micro-operation cache | Jared W. Stark, IV, Franck Sala, Michael Tal, Gil Shmueli, Adrian Flesler | 2020-03-03 |
| 10467011 | Thread pause processors, methods, systems, and instructions | Zeev Sperber, Michael Mishaeli, Stanislav Shwartsman, Lev Makovsky, Adi Yoaz +1 more | 2019-11-05 |
| 10402263 | Accelerating memory fault resolution by performing fast re-fetching | Zeev Sperber, Stanislav Shwartsman, Jared W. Stark, IV, Igor Yanover, George Leifman | 2019-09-03 |
| 10095522 | Instruction and logic for register based hardware memory renaming | Kamil Garifullin, Stanislav Shwartsman, Zeev Sperber, Pavel I. Kryukov, Andrey Kluchnikov +4 more | 2018-10-09 |
| 9690591 | System and method for fusing instructions queued during a time window defined by a delay counter | Ido Ouziel, Robert Valentine, Ron Gabor, Pankaj Raghuvanshi | 2017-06-27 |
| 9678807 | Hybrid threading | Alexander Gendler | 2017-06-13 |
| 9552169 | Apparatus and method for efficient memory renaming prediction using virtual registers | Jared W. Stark, IV, Kamil Garifullin, Franck Sala, Pavel I. Kryukov, Stanislav Shwartsman | 2017-01-24 |
| 9448879 | Apparatus and method for implement a multi-level memory hierarchy | Theodros Yigzaw, Oded Lempel, Hisham Shafi, Geeyarpuram N. Santhanakrishnan, Jose A. Vargas +6 more | 2016-09-20 |