Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417187 | Multi-key cryptographic memory protection | Siddhartha Chhabra, Hormuzd M. Khosravi, Gideon Gerzon, Barry E. Huntley, Gilbert Neiger +4 more | 2025-09-16 |
| 12021980 | Restricting usage of encryption keys by untrusted software | Arie Aharon, Dror Caspi, Baruch Chaikin, Jacob Doweck, Gideon Gerzon +7 more | 2024-06-25 |
| 11900115 | Apparatus and method to identify the source of an interrupt | Ashok Raj, Andreas Kleen, Gilbert Neiger, Beeman C. Strong, Jason W. Brandt +4 more | 2024-02-13 |
| 11775447 | System, apparatus and method for page granular, software controlled multiple key memory encryption | David M. Durham, Siddhartha Chhabra, Amy L. Santoni, Gilbert Neiger, Barry E. Huntley +6 more | 2023-10-03 |
| 11687654 | Providing isolation in virtualized systems using trust domains | Ravi L. Sahita, Baiju V. Patel, Barry E. Huntley, Gilbert Neiger, Hormuzd M. Khosravi +5 more | 2023-06-27 |
| 11614939 | Apparatus and method to identify the source of an interrupt | Ashok Raj, Andreas Kleen, Gilbert Neiger, Beeman C. Strong, Jason W. Brandt +4 more | 2023-03-28 |
| 11461244 | Co-existence of trust domain architecture with multi-key total memory encryption technology in servers | Arie Aharon, Dror Caspi, Baruch Chaikin, Jacob Doweck, Gideon Gerzon +8 more | 2022-10-04 |
| 11422811 | Restartable cache write-back and invalidation | Gideon Gerzon, Dror Caspi, Arie Aharon | 2022-08-23 |
| 11176059 | System, apparatus and method for page granular,software controlled multiple key memory encryption | David M. Durham, Siddhartha Chhabra, Amy L. Santoni, Gilbert Neiger, Barry E. Huntley +6 more | 2021-11-16 |
| 11139967 | Restricting usage of encryption keys by untrusted software | Arie Aharon, Dror Caspi, Baruch Chaikin, Jacob Doweck, Gideon Gerzon +7 more | 2021-10-05 |
| 11048512 | Apparatus and method to identify the source of an interrupt | Ashok Raj, Andreas Kleen, Gilbert Neiger, Beeman C. Strong, Jason W. Brandt +4 more | 2021-06-29 |
| 11029953 | Branch prediction unit in service of short microcode flows | Michael Mishaeli, Jared W. Stark, IV | 2021-06-08 |
| 10867092 | Avoiding asynchronous enclave exits based on requests to invalidate translation lookaside buffer entries | Dror Caspi | 2020-12-15 |
| 10838722 | Restartable cache write-back and invalidation | Gideon Gerzon, Dror Caspi, Arie Aharon | 2020-11-17 |
| 10657071 | System, apparatus and method for page granular, software controlled multiple key memory encryption | David M. Durham, Siddhartha Chhabra, Amy L. Santoni, Gilbert Neiger, Barry E. Huntley +6 more | 2020-05-19 |
| 10649783 | Multicore system for fusing instructions queued during a dynamically adjustable time window | Lihu Rappoport, Robert Valentine, Ron Gabor, Pankaj Raghuvanshi | 2020-05-12 |
| 10223121 | Method and apparatus for supporting quasi-posted loads | Raanan Sade, Jacob Doweck | 2019-03-05 |
| 10216662 | Hardware mechanism for performing atomic actions on remote processors | Michael Mishaeli, Baruch Chaikin, Yoav Zach | 2019-02-26 |
| 9858411 | Execution profiling mechanism | Ravi L. Sahita, Xiaoning Li, Barry E. Huntley, Ofer Levy, Vedvyas Shanbhogue +3 more | 2018-01-02 |
| 9792222 | Validating virtual address translation by virtual machine monitor utilizing address validation structure to validate tentative guest physical address and aborting based on flag in extended page table requiring an expected guest physical address in the address validation structure | Ravi L. Sahita, Gilbert Neiger, David M. Durham, Vedvyas Shanbhogue, Michael LeMay +3 more | 2017-10-17 |
| 9690591 | System and method for fusing instructions queued during a time window defined by a delay counter | Lihu Rappoport, Robert Valentine, Ron Gabor, Pankaj Raghuvanshi | 2017-06-27 |
| 9335943 | Method and apparatus for fine grain memory protection | Ravi L. Sahita, Vedvyas Shanbhogue, Gilbert Neiger, Jonathan M. Edwards, Barry E. Huntley +4 more | 2016-05-10 |
| 8782374 | Method and apparatus for inclusion of TLB entries in a micro-op cache of a processor | Lihu Rappoport, Chen Koren, Franck Sala, Oded Lempel, Ron Gabor +2 more | 2014-07-15 |
| 8127085 | Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor | Lihu Rappoport, Chen Koren, Franck Sala, Oded Lempel, Ilhyun Kim +3 more | 2012-02-28 |
| 8103831 | Efficient method and apparatus for employing a micro-op cache in a processor | Lihu Rappoport, Bob Valentine, Stephan Jourdan, Yoav Almog, Franck Sala +2 more | 2012-01-24 |