Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12287843 | Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements | Dan Baum, Elmoustapha Ould-Ahmed-Vall, Michael Espig, Christopher J. Hughes, Raanan Sade +3 more | 2025-04-29 |
| 11847185 | Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements | Dan Baum, Elmoustapha Ould-Ahmed-Vall, Michael Espig, Christopher J. Hughes, Raanan Sade +3 more | 2023-12-19 |
| 11513893 | Concurrent compute and ECC for in-memory matrix vector operations | Somnath Paul, Charles Augustine, George Shchupak, Muhammad M. Khellah | 2022-11-29 |
| 11450672 | Ultra-deep compute static random access memory with high compute throughput and multi-directional data propagation | Charles Augustine, Somnath Paul, Muhammad M. Khellah | 2022-09-20 |
| 10929503 | Apparatus and method for a masked multiply instruction to support neural network pruning operations | Omid Azizi, Nitin N. Garegrat | 2021-02-23 |
| 10620951 | Matrix multiplication acceleration of sparse matrices using column folding and squeezing | Omid Azizi, Guy Boudoukh, Tony L. Werner, Andrew Yang, Michael Rotzin +1 more | 2020-04-14 |
| 10509846 | Accelerator for processing data | Dan Baum | 2019-12-17 |
| 9448879 | Apparatus and method for implement a multi-level memory hierarchy | Theodros Yigzaw, Oded Lempel, Hisham Shafi, Geeyarpuram N. Santhanakrishnan, Jose A. Vargas +6 more | 2016-09-20 |
| 9348591 | Multi-level tracking of in-use state of cache lines | Ilhyun Kim, Alexandre J. Farcy, Robert L. Hinton, Choon Wei Khor, Lihu Rappoport | 2016-05-24 |
| 8782374 | Method and apparatus for inclusion of TLB entries in a micro-op cache of a processor | Lihu Rappoport, Franck Sala, Oded Lempel, Ido Ouziel, Ron Gabor +2 more | 2014-07-15 |
| 8433850 | Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor | Lihu Rappoport, Franck Sala, Ilhyun Kim, Lior Libis, Ron Gabor +1 more | 2013-04-30 |
| 8127085 | Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor | Lihu Rappoport, Franck Sala, Oded Lempel, Ido Ouziel, Ilhyun Kim +3 more | 2012-02-28 |