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USPTO Patent Rankings Data through Dec 31, 2025
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Chen Koren — 12 Patents

Intel: 12 patents #3,451 of 30,777Top 15%
Overall (All Time): #396,045 of 4,157,543Top 10%
12 Patents All Time
Chen Koren has been granted 12 US patents while listed as an inventor at Intel. The first was granted in 2012 and the most recent in April 2025. Chen Koren ranks #396,045 of 4,157,543 US inventors in our database (top 9.5%). Patent records list Chen Koren in Hadera, CA, IL.

Issued Patents All Time

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12287843 Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements Dan Baum, Elmoustapha Ould-Ahmed-Vall, Michael Espig, Christopher J. Hughes, Raanan Sade +3 more 2025-04-29
11847185 Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements Dan Baum, Elmoustapha Ould-Ahmed-Vall, Michael Espig, Christopher J. Hughes, Raanan Sade +3 more 2023-12-19 $50,836,000
11513893 Concurrent compute and ECC for in-memory matrix vector operations Somnath Paul, Charles Augustine, George Shchupak, Muhammad M. Khellah 2022-11-29 $14,086,000
11450672 Ultra-deep compute static random access memory with high compute throughput and multi-directional data propagation Charles Augustine, Somnath Paul, Muhammad M. Khellah 2022-09-20 $15,654,000
10929503 Apparatus and method for a masked multiply instruction to support neural network pruning operations Omid Azizi, Nitin N. Garegrat 2021-02-23 $31,062,000
10620951 Matrix multiplication acceleration of sparse matrices using column folding and squeezing Omid Azizi, Guy Boudoukh, Tony L. Werner, Andrew Yang, Michael Rotzin +1 more 2020-04-14 $33,667,000
10509846 Accelerator for processing data Dan Baum 2019-12-17 $31,829,000
9448879 Apparatus and method for implement a multi-level memory hierarchy Theodros Yigzaw, Oded Lempel, Hisham Shafi, Geeyarpuram N. Santhanakrishnan, Jose A. Vargas +6 more 2016-09-20 $10,814,000
9348591 Multi-level tracking of in-use state of cache lines Ilhyun Kim, Alexandre J. Farcy, Robert L. Hinton, Choon Wei Khor, Lihu Rappoport 2016-05-24 $13,693,000
8782374 Method and apparatus for inclusion of TLB entries in a micro-op cache of a processor Lihu Rappoport, Franck Sala, Oded Lempel, Ido Ouziel, Ron Gabor +2 more 2014-07-15 $14,407,000
8433850 Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor Lihu Rappoport, Franck Sala, Ilhyun Kim, Lior Libis, Ron Gabor +1 more 2013-04-30 $19,607,000
8127085 Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor Lihu Rappoport, Franck Sala, Oded Lempel, Ido Ouziel, Ilhyun Kim +3 more 2012-02-28 $20,590,000