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Multi-level tracking of in-use state of cache lines |
Ilhyun Kim, Chen Koren, Alexandre J. Farcy, Choon Wei Khor, Lihu Rappoport |
2016-05-24 |
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Hiding instruction cache miss latency by running tag lookups ahead of the instruction accesses |
Ilhyun Kim, Alexandre J. Farcy, Choon Wei Khor |
2015-10-13 |
| 9146745 |
Method and apparatus for partitioned pipelined execution of multiple execution threads |
Stephan Jourdan |
2015-09-29 |
| 7797683 |
Decoupling the number of logical threads from the number of simultaneous physical threads in a processor |
Per Hammarlund, Stephan Jourdan, Pierre Michaud, Alexandre J. Farcy, Morris Marden +1 more |
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Overriding a static prediction with a level-two predictor |
Mark Charles Davis, Stephan Jourdan, Boyd Phelps |
2009-05-12 |
| 7454596 |
Method and apparatus for partitioned pipelined fetching of multiple execution threads |
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2008-11-18 |