IK

Ilhyun Kim

IN Intel: 10 patents #4,046 of 30,777Top 15%
Apple: 3 patents #7,422 of 18,612Top 40%
LG: 3 patents #10,792 of 26,165Top 45%
LC Lsis Co.: 1 patents #300 of 527Top 60%
Overall (All Time): #263,502 of 4,157,543Top 7%
17
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12373215 Using a next fetch predictor circuit with short branches and return fetch groups Niket K. Choudhary, Mary D. Brown, Ethan Schuchman, Ronald P. Hall, Ian D. Kountanis +3 more 2025-07-29
12353882 Next fetch prediction using history Pruthivi Vuyyuru, Niket K. Choudhary, Ian D. Kountanis 2025-07-08
12265823 Trace cache with filter for internal control transfer inclusion Niket K. Choudhary, Muawya M. Al-Otoom, Pruthivi Vuyyuru, Ronald P. Hall 2025-04-01
12256036 Mobile terminal Changhwan Choi 2025-03-18
10453637 Direct current air circuit breaker Seungpil Yang, Sangchul Lee, Youngkook Kim 2019-10-22
10409611 Apparatus and method for transactional memory and lock elision including abort and end instructions to abort or commit speculative execution Martin G. Dixon, Ravi Rajwar, Konrad K. Lai, Robert S. Chappell, Rajesh S. Parthasarathy +4 more 2019-09-10
10409612 Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative execution Martin G. Dixon, Ravi Rajwar, Konrad K. Lai, Robert S. Chappell, Rajesh S. Parthasarathy +4 more 2019-09-10
9524191 Apparatus including a stall counter to bias processing element selection, and masks to allocate reservation unit entries to one or more processing elements Morris Marden, Matthew C. Merten, Alexandre J. Farcy, Avinash Sodani, James Hadley 2016-12-20
9521241 Mobile terminal and method of controlling the same Soyeon YIM, Jonghoon Kim, Jinhae CHOI, Bonjoon KOO, Youngjoon KIM 2016-12-13
9348591 Multi-level tracking of in-use state of cache lines Chen Koren, Alexandre J. Farcy, Robert L. Hinton, Choon Wei Khor, Lihu Rappoport 2016-05-24
9158696 Hiding instruction cache miss latency by running tag lookups ahead of the instruction accesses Alexandre J. Farcy, Choon Wei Khor, Robert L. Hinton 2015-10-13
8990868 Display device and method for displaying contents on the same Jungbin Lee, Ryoung Kim, Jun Hee Kim, Ubeom HEO, Jiwan Nam +5 more 2015-03-24
8521993 Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor Morris Marden, Matthew C. Merten, Alexandre J. Farcy, Avinash Sodani, James Hadley 2013-08-27
8438369 Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor Morris Marden, Matthew C. Merten, Alexandre J. Farcy, Avinash Sodani, James Hadley 2013-05-07
8433850 Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor Lihu Rappoport, Chen Koren, Franck Sala, Lior Libis, Ron Gabor +1 more 2013-04-30
8127085 Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor Lihu Rappoport, Chen Koren, Franck Sala, Oded Lempel, Ido Ouziel +3 more 2012-02-28
7925834 Tracking temporal use associated with cache evictions Peter J. Smith, Mongkol Ekpanyapong, Harikrishna B. Baliga 2011-04-12