Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423106 | Next fetch predictor for trace cache | Niket K. Choudhary, Pruthivi Vuyyuru | 2025-09-23 |
| 12288070 | Program counter zero-cycle loads | Conrado Blasco, Deepankar Duggal, Ethan Schuchman, Ian D. Kountanis, Kulin N. Kothari +1 more | 2025-04-29 |
| 12265823 | Trace cache with filter for internal control transfer inclusion | Ilhyun Kim, Niket K. Choudhary, Pruthivi Vuyyuru, Ronald P. Hall | 2025-04-01 |
| 12236244 | Multi-degree branch predictor | Wei-Han Lien, Ian D. Kountanis, Niket K. Choudhary, Pruthivi Vuyyuru | 2025-02-25 |
| 11630670 | Multi-table signature prefetch | Douglas C. Holman, Ian D. Kountanis, Amit Kumar | 2023-04-18 |
| 11416254 | Zero cycle load bypass in a decode group | Deepankar Duggal, Kulin N. Kothari, Conrado Blasco | 2022-08-16 |
| 11379240 | Indirect branch predictor based on register operands | Ian D. Kountanis, Conrado Blasco, Haoyan Jia, Amit Kumar | 2022-07-05 |
| 11200062 | History file for previous register mapping storage and last reference indication | Deepankar Duggal, Conrado Blasco, Richard F. Russo | 2021-12-14 |
| 10838729 | System and method for predicting memory dependence when a source register of a push instruction matches the destination register of a pop instruction | Conrado Blasco, Deepankar Duggal, Kulin N. Kothari, Richard F. Russo | 2020-11-17 |
| 10719327 | Branch prediction system | Ian D. Kountanis, Conrado Blasco | 2020-07-21 |
| 10691457 | Register allocation using physical register file bypass | Ian D. Kountanis | 2020-06-23 |
| 10209989 | Accelerated interlane vector reduction instructions | Paul Caprioli, Abhay S. Kanhere, Jeffrey J. Cook | 2019-02-19 |
| 9652234 | Instruction and logic to control transfer in a partial binary translation system | Paul Caprioli, Martin G. Dixon, Brett L. Toll, Omar M. Shaikh | 2017-05-16 |
| 9632791 | Cache for patterns of instructions with multiple forward control transfers | Ian D. Kountanis, Ronald P. Hall, Michael L. Karm | 2017-04-25 |
| 9588766 | Accelerated interlane vector reduction instructions | Paul Caprioli, Abhay S. Kanhere, Jeffrey J. Cook | 2017-03-07 |
| 9542191 | Hardware profiling mechanism to enable page level automatic binary translation | Paul Caprioli, Matthew C. Merten, Omar M. Shaikh, Abhay S. Kanhere, Suresh Srinivas +3 more | 2017-01-10 |
| 9411739 | System, method and apparatus for improving transactional memory (TM) throughput using TM region indicators | Omar M. Shaikh, Ravi Rajwar, Paul Caprioli | 2016-08-09 |
| 9292294 | Detection of memory address aliasing and violations of data dependency relationships | Paul Caprioli, Ryan Carlson, Ho-Seop Kim, Omar M. Shaikh | 2016-03-22 |
| 8826257 | Memory disambiguation hardware to support software binary translation | Paul Caprioli, Abhay S. Kanhere, Arvind Krishnaswamy, Omar M. Shaikh | 2014-09-02 |
| 8078852 | Predictors with adaptive prediction threshold | Timothy H. Heil, Anil Krishna, Ken V. Vu | 2011-12-13 |