| 12430137 |
Processor with opportunistic bypass of dispatch buffer and reservation station |
Divyansh Jagota, Manan Salvi, Vignyan Kothinti |
2025-09-30 |
|
| 12236244 |
Multi-degree branch predictor |
Muawya M. Al-Otoom, Ian D. Kountanis, Niket K. Choudhary, Pruthivi Vuyyuru |
2025-02-25 |
|
| 12067399 |
Conditional instructions prediction |
Ian D. Kountanis, Douglas C. Holman, Pruthivi Vuyyuru, Ethan Schuchman, Niket K. Choudhary +2 more |
2024-08-20 |
$206,773,000 |
| 11829763 |
Early load execution via constant address and stride prediction |
Yuan C. Chou, Viney Gautam, Kulin N. Kothari, Mridul Agarwal |
2023-11-28 |
$171,025,000 |
| 11809874 |
Conditional instructions distribution and execution on pipelines having different latencies for mispredictions |
Ethan Schuchman, Niket K. Choudhary, Kulin N. Kothari, Haoyan Jia, Ian D. Kountanis +2 more |
2023-11-07 |
$200,618,000 |
| 11003233 |
Dynamic voltage and frequency management based on active processors |
Jong-Suk Lee, Daniel C. Murray |
2021-05-11 |
$296,431,000 |
| 10303238 |
Dynamic voltage and frequency management based on active processors |
Jong-Suk Lee, Daniel C. Murray |
2019-05-28 |
$54,822,000 |
| 9959120 |
Persistent relocatable reset vector for processor |
Josh P. de Cesare, Gerard R. Williams, III, Michael J. Smith |
2018-05-01 |
$111,912,000 |
| 9703354 |
Dynamic voltage and frequency management based on active processors |
Jong-Suk Lee, Daniel C. Murray |
2017-07-11 |
$63,067,000 |
| 9684516 |
Register renamer that handles multiple register sizes aliased to the same storage locations |
— |
2017-06-20 |
$70,324,000 |
| 9626185 |
IT instruction pre-decode |
Shyam Sundar, Ian D. Kountanis, Conrado Blasco-Allue, Gerard R. Williams, III, Ramesh Gunna |
2017-04-18 |
$63,955,000 |
| 9541984 |
L2 flush and memory fabric teardown |
Shih-Chieh Wen, Jason M. Kassoff |
2017-01-10 |
$61,338,000 |
| 9411360 |
Method to manage current during clock frequency changes |
Jong-Suk Lee, Shih-Chieh Wen |
2016-08-09 |
$44,625,000 |
| 9383806 |
Multi-core processor instruction throttling |
Gerard R. Williams, III, Rohit Kumar, Sandeep Gupta, Suresh Periyacheri, Shih-Chieh Wen |
2016-07-05 |
$80,430,000 |
| 9311100 |
Usefulness indication for indirect branch prediction training |
Sandeep Gupta, Shyam Sundar, Gerard R. Williams, III, Conrado Blasco-Allue |
2016-04-12 |
$59,139,000 |
| 9304573 |
Dynamic voltage and frequency management based on active processors |
Jong-Suk Lee, Daniel C. Murray |
2016-04-05 |
$46,684,000 |
| 9294103 |
Pre-program of clock generation circuit for faster lock coming out of reset |
Jong-Suk Lee, Shih-Chieh Wen, Toshinari Takayanagi |
2016-03-22 |
$58,412,000 |
| 9280471 |
Mechanism for sharing private caches in a SoC |
Manu Gulati, Harshavardhan Kaushikkar, Gurjeet S. Saund, Gerard R. Williams, III, Sukalpa Biswas +2 more |
2016-03-08 |
$72,237,000 |
| 9158541 |
Register renamer that handles multiple register sizes aliased to the same storage locations |
— |
2015-10-13 |
$69,675,000 |
| 8566528 |
Combining write buffer with dynamically adjustable flush metrics |
Peter J. Bannon, Andrew J. Beaumont-Smith, Ramesh Gunna, Brian P. Lilly, Jaidev P. Patwardhan +2 more |
2013-10-22 |
$104,740,000 |
| 8514873 |
Advanced telecommunications router and crossbar switch controller |
Brian Hang Wai Yang, Kai-Yeung (Sunny) Siu, Mizanur Rahman, Gaurav Singh |
2013-08-20 |
|
| 8352685 |
Combining write buffer with dynamically adjustable flush metrics |
Peter J. Bannon, Andrew J. Beaumont-Smith, Ramesh Gunna, Brian P. Lilly, Jaidev P. Patwardhan +2 more |
2013-01-08 |
$91,537,000 |
| 8255670 |
Replay reduction for power saving |
Po-Yung Chang, Jesse Pan, Ramesh Gunna, Tse-Yu Yeh, James B. Keller |
2012-08-28 |
$72,244,000 |
| 8219787 |
Early release of resources by proceeding to retire store operations from exception reporting stage but keeping in load/store queue |
Po-Yung Chang |
2012-07-10 |
$155,116,000 |
| 7996662 |
Floating point status/control register encodings for speculative register field |
Daniel C. Murray, Junji Sugisawa |
2011-08-09 |
$65,800,000 |
