Issued Patents All Time
Showing 1–25 of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12229052 | System for prefetching data into a cache | Ramkumar Srinivasan, Varun Palivela | 2025-02-18 |
| 12135649 | System for prefetching data into a cache | Ramkumar Srinivasan, Varun Palivela | 2024-11-05 |
| 11972140 | Hashing with soft memory folding | Steven Fishwick, Jeffry E. Gonion, Per Hammarlund, Eran Tamari, Lior Zimet | 2024-04-30 |
| 11941428 | Ensuring transactional ordering in I/O agent | Sagi Lahav, Lital Levy-Rubin, Gaurav Garg, Samer Nassar, Per Hammarlund +3 more | 2024-03-26 |
| 11868192 | Systems and methods for coherent power management | Joseph T. DiBene, II, Inder M. Sodhi, Keith Cox | 2024-01-09 |
| 11803471 | Scalable system on a chip | Per Hammarlund, Lior Zimet, Sergio Kolor, Sagi Lahav, James Vash +11 more | 2023-10-31 |
| 11567861 | Hashing with soft memory folding | Steven Fishwick, Jeffry E. Gonion, Per Hammarlund, Eran Tamari, Lior Zimet | 2023-01-31 |
| 11550716 | I/O agent | Gaurav Garg, Sagi Lahav, Lital Levy-Rubin, Samer Nassar, Per Hammarlund +4 more | 2023-01-10 |
| 11204636 | Systems and methods for coherent power management | Joseph T. DiBene, II, Inder M. Sodhi, Keith Cox | 2021-12-21 |
| 11042373 | Computation engine that operates in matrix and vector modes | Eric Bainville, Jeffry E. Gonion, Ali Sazegari | 2021-06-22 |
| 10867031 | Marking valid return targets | Gregory D. Hughes, Conrado Blasco, Jacques Anthony Vidrine, Jeffry E. Gonion, Timothy R. Paaske +1 more | 2020-12-15 |
| 10845856 | Reduced power operation using stored capacitor energy | Joseph T. DiBene, II, Inder M. Sodhi | 2020-11-24 |
| 10831488 | Computation engine with extract instructions to minimize memory access | Eric Bainville, Jeffry E. Gonion, Ali Sazegari, Andrew J. Beaumont-Smith | 2020-11-10 |
| 10769065 | Systems and methods for performing memory compression | Ali Sazegari, Charles E. Tucker, Jeffry E. Gonion, Chris C. Lee | 2020-09-08 |
| 10754649 | Computation engine that operates in matrix and vector modes | Eric Bainville, Jeffry E. Gonion, Ali Sazegari | 2020-08-25 |
| 10621100 | Unified prefetch circuit for multi-level caches | Stephan G. Meier, Tyler J. Huberty, Pradeep Kanapathipillai | 2020-04-14 |
| 10437595 | Load/store dependency predictor optimization for replayed loads | Pradeep Kanapathipillai, Stephan G. Meier, Mridul Agarwal, Kulin N. Kothari | 2019-10-08 |
| 10423209 | Systems and methods for coherent power management | Joseph T. DiBene, II, Inder M. Sodhi, Keith Cox | 2019-09-24 |
| 10401945 | Processor including multiple dissimilar processor cores that implement different portions of instruction set architecture | David Williamson, James Nolan Hardage, Richard F. Russo | 2019-09-03 |
| 10331558 | Systems and methods for performing memory compression | Ali Sazegari, Charles E. Tucker, Jeffry E. Gonion, Chris C. Lee | 2019-06-25 |
| 10289191 | Processor including multiple dissimilar processor cores | David Williamson | 2019-05-14 |
| 10281965 | Reduced power operation using stored capacitor energy | Joseph T. DiBene, II, Inder M. Sodhi | 2019-05-07 |
| 10180905 | Unified prefetch circuit for multi-level caches | Stephan G. Meier, Tyler J. Huberty, Pradeep Kanapathipillai | 2019-01-15 |
| 9996348 | Zero cycle load | John H. Mylius, Conrade Blasco-Allue | 2018-06-12 |
| 9959120 | Persistent relocatable reset vector for processor | Josh P. de Cesare, Michael J. Smith, Wei-Han Lien | 2018-05-01 |