Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12321746 | DSB operation with excluded region | Jeff Gonion, John H. Kelm, James Vash, Pradeep Kanapathipillai, Gideon N. Levinsky +2 more | 2025-06-03 |
| 12314200 | Scalable interrupts | Jeffrey E. Gonion, Charles E. Tucker, Tal Kuzi, Richard F. Russo, Christopher M. Tsay +3 more | 2025-05-27 |
| 12306762 | Deny list for a memory prefetcher circuit | Tyler J. Huberty, Eric J. Furbish, Peter G. Soderquist, Sandeep Gupta, Stephen G. Meier +4 more | 2025-05-20 |
| 12307256 | Livelock detection and resolution using oldest operation tracking | Deepankar Duggal, Haoyan Jia, Richard F. Russo, Debasish Chandra, Yanran Yang | 2025-05-20 |
| 12298915 | Hierarchical store queue circuit | Nikhil Gupta, Gideon N. Levinsky, Kulin N. Kothari, Pankaj Lnu | 2025-05-13 |
| 12229561 | Processing of data synchronization barrier instructions | Madhu Sudan Hari, Kulin N. Kothari, John D. Pape, Niket K. Choudhary | 2025-02-18 |
| 12067398 | Shared learning table for load value prediction and load address prediction | Yuan C. Chou, Debasish Chandra, Haoyan Jia | 2024-08-20 |
| 12045615 | Processing of synchronization barrier instructions | Deepankar Duggal, Kulin N. Kothari, Chang Xu, Yanran Yang, Richard F. Russo +2 more | 2024-07-23 |
| 12007920 | Scalable interrupts | Jeffrey E. Gonion, Charles E. Tucker, Tal Kuzi, Richard F. Russo, Christopher M. Tsay +3 more | 2024-06-11 |
| 11914511 | Decoupling atomicity from operation size | Francesco Spadini, Gideon N. Levinsky | 2024-02-27 |
| 11829763 | Early load execution via constant address and stride prediction | Yuan C. Chou, Viney Gautam, Wei-Han Lien, Kulin N. Kothari | 2023-11-28 |
| 11720360 | DSB operation with excluded region | Jeff Gonion, John H. Kelm, James Vash, Pradeep Kanapathipillai, Gideon N. Levinsky +2 more | 2023-08-08 |
| 11630789 | Scalable interrupts | Jeffrey E. Gonion, Charles E. Tucker, Tal Kuzi, Richard F. Russo, Christopher M. Tsay +3 more | 2023-04-18 |
| 11500638 | Hardware compression and decompression engine | Aditya Kesiraju, James Vash, Pradeep Kanapathipillai, Zhaoming Hu, Tyler J. Huberty +1 more | 2022-11-15 |
| 11175917 | Buffer for replayed loads in parallel with reservation station for rapid rescheduling | Kulin N. Kothari, Nikhil Gupta | 2021-11-16 |
| 11166212 | Elevation based mode switch for 5G based aerial UE | Akash Kumar, Hargovind Prasad BANSAL | 2021-11-02 |
| 11099990 | Managing serial miss requests for load operations in a non-coherent memory system | Gideon N. Levinsky, Brian R. Mestan, Deepak Limaye | 2021-08-24 |
| 10983801 | Load/store ordering violation management | Kulin N. Kothari | 2021-04-20 |
| 10628164 | Branch resolve pointer optimization | Kulin N. Kothari, Aditya Kesiraju, Deepankar Duggal, Sean M. Reynolds | 2020-04-21 |
| 10437595 | Load/store dependency predictor optimization for replayed loads | Pradeep Kanapathipillai, Stephan G. Meier, Gerard R. Williams, III, Kulin N. Kothari | 2019-10-08 |
| 10402334 | Prefetch circuit for a processor with pointer optimization | Stephan G. Meier | 2019-09-03 |
| 10356755 | Intelligent resource assignment to increase throughput in multiple input multiple output (MIMO) and carrier aggregation (CA) capable devices | Akash Kumar, Pengkai Zhao, Narayanan Pazhedath Illath, Hargovind Prasad BANSAL, Vijayvaradharaj Tirucherai Muralidharan +2 more | 2019-07-16 |
| 10228951 | Out of order store commit | Kulin N. Kothari, Pradeep Kanapathipillai | 2019-03-12 |
| 10133571 | Load-store unit with banked queue | Aditya Kesiraju, Pradeep Kanapathipillai, Sean M. Reynolds | 2018-11-20 |
| 9971694 | Prefetch circuit for a processor with pointer optimization | Stephan G. Meier | 2018-05-15 |