Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411748 | Converting telemetry values into common data formats in a processor-based system in an integrated circuit (IC) chip | Sagar Koorapati, Alon Naveh | 2025-09-09 |
| 12321746 | DSB operation with excluded region | Jeff Gonion, John H. Kelm, James Vash, Mridul Agarwal, Gideon N. Levinsky +2 more | 2025-06-03 |
| 12174785 | Coprocessors with bypass optimization, variable grid architecture, and fused vector operations | Aditya Kesiraju, Andrew J. Beaumont-Smith, Boris S. Alvarez-Heredia, Ran A. Chachick | 2024-12-24 |
| 11914524 | Latency management in synchronization events | Adrian Montero, Huzefa Sanjeliwala, Paul Kitchin, Prarthna Santhanakrishnan, Conrado Blasco | 2024-02-27 |
| 11797045 | Dynamic voltage and frequency scaling (DVFS) within processor clusters | Jonathan Masters, Manu Gulati, Nitin Makhija | 2023-10-24 |
| 11720360 | DSB operation with excluded region | Jeff Gonion, John H. Kelm, James Vash, Mridul Agarwal, Gideon N. Levinsky +2 more | 2023-08-08 |
| 11500638 | Hardware compression and decompression engine | Aditya Kesiraju, James Vash, Mridul Agarwal, Zhaoming Hu, Tyler J. Huberty +1 more | 2022-11-15 |
| 11221962 | Unified address translation | Jeffry E. Gonion, Bernard J. Semeria, Michael James Elliott Swift, David Williamson | 2022-01-11 |
| 10990159 | Architected state retention for a frequent operating state switching processor | Bernard J. Semeria, John H. Mylius, Richard F. Russo, Shih-Chieh Wen, Richard H. Larson | 2021-04-27 |
| 10725928 | Translation lookaside buffer invalidation by range | Brian R. Mestan, Joshua William Smith | 2020-07-28 |
| 10621100 | Unified prefetch circuit for multi-level caches | Stephan G. Meier, Tyler J. Huberty, Gerard R. Williams, III | 2020-04-14 |
| 10437595 | Load/store dependency predictor optimization for replayed loads | Stephan G. Meier, Gerard R. Williams, III, Mridul Agarwal, Kulin N. Kothari | 2019-10-08 |
| 10228951 | Out of order store commit | Kulin N. Kothari, Mridul Agarwal | 2019-03-12 |
| 10180905 | Unified prefetch circuit for multi-level caches | Stephan G. Meier, Tyler J. Huberty, Gerard R. Williams, III | 2019-01-15 |
| 10133571 | Load-store unit with banked queue | Aditya Kesiraju, Mridul Agarwal, Sean M. Reynolds | 2018-11-20 |
| 10037073 | Execution unit power management | Edvin Catovic, Rajat Goel, Richard F. Russo, Matthew R. Johnson, Shingo Suzuki +2 more | 2018-07-31 |
| 9852084 | Access permissions modification | Peter G. Soderquist, Bernard J. Semeria, Joshua P. de Cesare, David Williamson, Gerard R. Williams, III | 2017-12-26 |
| 9710268 | Reducing latency for pointer chasing loads | Stephan G. Meier, Sandeep Gupta | 2017-07-18 |
| 9535695 | Completing load and store instructions in a weakly-ordered memory model | John H. Mylius, Rajat Goel, Hari Kannan | 2017-01-03 |
| 9501284 | Mechanism for allowing speculative execution of loads beyond a wait for event instruction | Richard F. Russo, Sandeep Gupta, Conrado Blasco | 2016-11-22 |
| 9494997 | Hierarchical clock control using hysterisis and threshold management | Kulin N. Kothari, Chetana N. Keltcher, Pankaj Raghuvanshi | 2016-11-15 |
| 9383995 | Load ordering in a weakly-ordered processor | Hari Kannan, Po-Yung Chang, Ming-Ta Hsu, Rajat Goel | 2016-07-05 |
| 9229866 | Delaying cache data array updates | Hari Kannan, Brian P. Lilly, Perumal R. Subramoniam | 2016-01-05 |
| 9131899 | Efficient handling of misaligned loads and stores | Hari Kannan, Greg M. Hess | 2015-09-15 |
| 9098418 | Coordinated prefetching based on training in hierarchically cached processors | Hari Kannan, Brian P. Lilly, Gerard R. Williams, III, Mahnaz Sadoughi-Yarandi, Perumal R. Subramoniam | 2015-08-04 |