Issued Patents All Time
Showing 25 most recent of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11221962 | Unified address translation | Jeffry E. Gonion, Bernard J. Semeria, Michael James Elliott Swift, Pradeep Kanapathipillai | 2022-01-11 |
| 11093249 | Methods for partially preserving a branch predictor state | Conrado Blasco, Brett S. Feero, Ian D. Kountanis, Shih-Chieh Wen | 2021-08-17 |
| 10922232 | Using cache memory as RAM with external access support | Brett S. Feero, David E. Kroesche | 2021-02-16 |
| 10402326 | Accessing memories in coherent and non-coherent domains in a computing system | Ronald P. Hall, Mahesh K. Reddy | 2019-09-03 |
| 10401945 | Processor including multiple dissimilar processor cores that implement different portions of instruction set architecture | Gerard R. Williams, III, James Nolan Hardage, Richard F. Russo | 2019-09-03 |
| 10289191 | Processor including multiple dissimilar processor cores | Gerard R. Williams, III | 2019-05-14 |
| 10223123 | Methods for partially saving a branch predictor state | Conrado Blasco, Brett S. Feero, Ian D. Kountanis, Shih-Chieh Wen | 2019-03-05 |
| 10007616 | Methods for core recovery after a cold start | Brett S. Feero, Jonathan J. Tyler, Mary D. Brown | 2018-06-26 |
| 9958932 | Processor including multiple dissimilar processor cores that implement different portions of instruction set architecture | Gerard R. Williams, III, James Nolan Hardage, Richard F. Russo | 2018-05-01 |
| 9898071 | Processor including multiple dissimilar processor cores | Gerard R. Williams, III | 2018-02-20 |
| 9852084 | Access permissions modification | Peter G. Soderquist, Pradeep Kanapathipillai, Bernard J. Semeria, Joshua P. de Cesare, Gerard R. Williams, III | 2017-12-26 |
| 9524011 | Instruction loop buffer with tiered power savings | Ronald P. Hall, Michael L. Karm, Ian D. Kountanis | 2016-12-20 |
| 8386754 | Renaming wide register source operand with plural short register source operands for select instructions to detect dependency fast with existing mechanism | Conrado Blasco Allue, James Nolan Hardage, Glen Andrew Harris, Robert Gregory McDonald | 2013-02-26 |
| 8255629 | Method and apparatus with data storage protocols for maintaining consistencies in parallel translation lookaside buffers | Paul Gilbert Meyer, Simon John Craske | 2012-08-28 |
| 8234489 | Set of system configuration registers having shadow register | James Nolan Hardage | 2012-07-31 |
| 8051275 | Result path sharing between a plurality of execution units within a processor | Conrado Blasco Allue | 2011-11-01 |
| 7774582 | Result bypassing to override a data hazard within a superscalar processor | Glen Andrew Harris, Stephen John Hill | 2010-08-10 |
| 7725695 | Branch prediction apparatus for repurposing a branch to instruction set as a non-predicted branch | Andrew James Booker, David John Butcher | 2010-05-25 |
| 7496899 | Preventing loss of traced information in a data processing apparatus | Stephen John Hill, Glen Andrew Harris | 2009-02-24 |
| 7437544 | Data processing apparatus and method for executing a sequence of instructions including a multiple iteration instruction | Ann Sekli Chin | 2008-10-14 |
| 7389459 | Provision of debug via a separate ring bus in a data processing apparatus | Conrado Blasco Allue, Stephen John Hill | 2008-06-17 |
| 7343481 | Branch prediction in a data processing system utilizing a cache of previous static predictions | — | 2008-03-11 |
| 7197671 | Generation of trace elements within a data processing apparatus | Andrew Brookfield Swaine | 2007-03-27 |
| 7093236 | Tracing out-of-order data | Andrew Brookfield Swaine, Paul Robert Gotch | 2006-08-15 |
| 7080289 | Tracing multiple data access instructions | Andrew Brookfield Swaine | 2006-07-18 |