Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11422821 | Age tracking for independent pipelines | Christopher M. Tsay, Mahesh K. Reddy | 2022-08-23 |
| 11080188 | Method to ensure forward progress of a processor in the presence of persistent external cache/TLB maintenance requests | Jonathan Y. Tong, Ronald P. Hall, Christopher L. Colletti, David E. Kroesche | 2021-08-03 |
| 10401945 | Processor including multiple dissimilar processor cores that implement different portions of instruction set architecture | David Williamson, Gerard R. Williams, III, Richard F. Russo | 2019-09-03 |
| 10372500 | Register allocation system | Christopher Scott Thomas, Christopher M. Tsay | 2019-08-06 |
| 9958932 | Processor including multiple dissimilar processor cores that implement different portions of instruction set architecture | David Williamson, Gerard R. Williams, III, Richard F. Russo | 2018-05-01 |
| 9946545 | Buffer store with a main store and and auxiliary store | Glen Andrew Harris, Mark Carpenter Glass | 2018-04-17 |
| 9928115 | Hardware migration between dissimilar cores | Daniel U. Becker, Christopher M. Tsay, Richard F. Russo, Shih-Chieh Wen, Richard H. Larson | 2018-03-27 |
| 9081581 | Size mis-match hazard detection | Conrado Blasco Allue, Glen Andrew Harris | 2015-07-14 |
| 9058179 | Retirement serialisation of status register access operations | — | 2015-06-16 |
| 8972701 | Setting zero bits in architectural register for storing destination operand of smaller size based on corresponding zero flag attached to renamed physical register | Glen Andrew Harris, Mark Carpenter Glass | 2015-03-03 |
| 8914615 | Mapping same logical register specifier for different instruction sets with divergent association to architectural register file using common address format | Glen Andrew Harris, Mark Carpenter Glass | 2014-12-16 |
| 8386754 | Renaming wide register source operand with plural short register source operands for select instructions to detect dependency fast with existing mechanism | Conrado Blasco Allue, David Williamson, Glen Andrew Harris, Robert Gregory McDonald | 2013-02-26 |
| 8250346 | Register renaming of a partially updated data granule | — | 2012-08-21 |
| 8234489 | Set of system configuration registers having shadow register | David Williamson | 2012-07-31 |
| 7146468 | Cache memory and method for handling effects of external snoops colliding with in-flight operations internally to the cache | — | 2006-12-05 |
| 7085885 | Apparatus and method for early cache miss detection | — | 2006-08-01 |
| 6636980 | System for launching data on a bus by using first clock for alternately selecting data from two data streams and using second clock for launching data thereafter | Gilles Gervais, David George Caffo, Stephen Douglas Weitzel | 2003-10-21 |
| 6449738 | Apparatus for bus frequency independent wrap I/O testing and method therefor | Fahd Hinedi, Lakshmikant Mamileti | 2002-09-10 |
| 6415362 | Method and system for write-through stores of varying sizes | Alexander Edward Okpisz, Thomas A. Petersen | 2002-07-02 |
| 6408361 | Autonomous way specific tag update | Thomas A. Petersen, Scott I. Remington | 2002-06-18 |
| 6332179 | Allocation for back-to-back misses in a directory based cache | Alexander Edward Okpisz | 2001-12-18 |
| 6269360 | Optimization of ordered stores on a pipelined bus via self-initiated retry | Thomas A. Petersen | 2001-07-31 |
| 6256713 | Bus optimization with read/write coherence including ordering responsive to collisions | Srinath Audityan, Thomas A. Petersen | 2001-07-03 |
| 6119204 | Data processing system and method for maintaining translation lookaside buffer TLB coherency without enforcing complete instruction serialization | Joseph Y. Chang, Jose M. Nunez, Thomas A. Petersen | 2000-09-12 |
| 6023737 | Multi-stage pipelined data coalescing for improved frequency operation | Thomas A. Petersen | 2000-02-08 |