JN

Jose M. Nunez

IBM: 10 patents #10,888 of 70,183Top 20%
FS Freeescale Semiconductor: 9 patents #343 of 3,767Top 10%
Motorola: 2 patents #4,475 of 12,470Top 40%
Overall (All Time): #223,830 of 4,157,543Top 6%
20
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9423972 Error recovery in a data processing system which implements partial writes James A. Welker 2016-08-23
9195625 Interconnect controller for a data processing device with transaction tag locking and method therefor Gus P. Ikonomopoulos, Thang Q. Nguyen, Kun Xu 2015-11-24
8300464 Method and circuit for calibrating data capture in a memory controller James A. Welker 2012-10-30
7613775 Network message filtering using hashing and pattern matching Carlos A. Greaves, Harold M. Martin, Thang Q. Nguyen 2009-11-03
7240041 Network message processing using inverse pattern matching Harold M. Martin, Carlos A. Greaves, Thang Q. Nguyen 2007-07-03
7181638 Method and apparatus for skewing data with respect to command on a DDR interface James A. Welker, Thomas L. Thomas, Jr. 2007-02-20
6937961 Performance monitor and method therefor Carlos Javier Cabral 2005-08-30
6898682 Automatic READ latency calculation without software intervention for a source-synchronous interface James A. Welker, Srinath Audityan, Robert Podnar 2005-05-24
6847990 Data transfer unit with support for multiple coherency granules Srinath Audityan, Marie Jeannette Sullivan 2005-01-25
6615323 Optimizing pipelined snoop processing Thomas A. Petersen, Marie Jeannette Sullivan 2003-09-02
6460133 Queue resource tracking in a multiprocessor system Thomas A. Petersen 2002-10-01
6430658 Local cache-to-cache transfers in a multiprocessor system Thomas A. Petersen 2002-08-06
6389516 Intervention ordering in a multiprocessor system Robert Podnar, Marie Jeannette Sullivan 2002-05-14
6338121 Data source arbitration in a multiprocessor system Thomas A. Petersen 2002-01-08
6275906 Coherency maintenance in a multiprocessor system Thomas A. Peterson, Marie Jeannette Sullivan 2001-08-14
6272601 Critical word forwarding in a multiprocessor system Thomas A. Petersen 2001-08-07
6272604 Contingent response apparatus and method for maintaining cache coherency Robert Podnar, Marie Jeannette Sullivan 2001-08-07
6249845 Method for supporting cache control instructions within a coherency granule Thomas A. Petersen 2001-06-19
6119204 Data processing system and method for maintaining translation lookaside buffer TLB coherency without enforcing complete instruction serialization Joseph Y. Chang, James Nolan Hardage, Thomas A. Petersen 2000-09-12
5835946 High performance implementation of the load reserve instruction in a superscalar microprocessor that supports multi-level cache organizations Michael S. Allen, Brad B. Beavers, Robert Alan Cargnoni, David W. Todd, Jen-Tian Yen 1998-11-10