Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12190936 | System and method for refreshing dynamic random access memory | Suhas Chakravarty | 2025-01-07 |
| 12124328 | Data processing system having a memory controller with inline error correction code (ECC) support | Diviya Jain | 2024-10-22 |
| 12124385 | Bandwidth allocation | Vaibhav Kumar, Rohit Kumar Kaul, Ankush Sethi | 2024-10-22 |
| 12072757 | Data processing system with tag-based queue management | Ankush Sethi, Rohit Kumar Kaul, Vaibhav Kumar, Jehoda Refaeli | 2024-08-27 |
| 11620184 | Runtime integrity checking for a memory system | Thomas E. Tkacik, Geoffrey Paul Waters, Mohit Mongia | 2023-04-04 |
| 11567676 | Inline encryption/decryption for a memory controller | Thomas E. Tkacik, Geoffrey Paul Waters, Mohit Mongia, Srdjan Coric | 2023-01-31 |
| 10819355 | Phase to digital converter | Firas N. Abughazaleh, David Gordon Bearden, Huy Nguyen, Venkatarama Mohanareddy Mooraka | 2020-10-27 |
| 10366005 | Memory interleave system and method therefor | Arup Chakraborty, Mazyar Razzaz | 2019-07-30 |
| 9437277 | Mechanism for data generation in data processing systems | Joshua E. Siegel | 2016-09-06 |
| 9437326 | Margin tool for double data rate memory systems | Mazyar Razzaz, Kenneth R. Burch | 2016-09-06 |
| 9423972 | Error recovery in a data processing system which implements partial writes | Jose M. Nunez | 2016-08-23 |
| 8572322 | Asynchronously scheduling memory access requests | Kun Xu, David B. Kramer | 2013-10-29 |
| 8300464 | Method and circuit for calibrating data capture in a memory controller | Jose M. Nunez | 2012-10-30 |
| 8117483 | Method to calibrate start values for write leveling in a memory system | Michael George | 2012-02-14 |
| 7957218 | Memory controller with skew control and method | — | 2011-06-07 |
| 7872494 | Memory controller calibration | Hector Sanchez, Joshua E. Siegel | 2011-01-18 |
| 7181638 | Method and apparatus for skewing data with respect to command on a DDR interface | Thomas L. Thomas, Jr., Jose M. Nunez | 2007-02-20 |
| 6898682 | Automatic READ latency calculation without software intervention for a source-synchronous interface | Srinath Audityan, Jose M. Nunez, Robert Podnar | 2005-05-24 |