Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12072757 | Data processing system with tag-based queue management | Ankush Sethi, Rohit Kumar Kaul, James A. Welker, Vaibhav Kumar | 2024-08-27 |
| 11769567 | Devices and methods for preventing errors and detecting faults within a memory device | Glenn C. Abeln, Jorge Arturo Corso Sarmiento | 2023-09-26 |
| 11645155 | Safe-stating a system interconnect within a data processing system | Arjun Pal Chowdhury, Nancy Hing-Che Amedeo | 2023-05-09 |
| 11334409 | Method and system for fault collection and reaction in system-on-chip | Hemant Nautiyal, Ankush Sethi, Shreya Singh | 2022-05-17 |
| 11069421 | Circuitry for checking operation of error correction code (ECC) circuitry | Nancy Hing-Che Amedeo, Quyen Pho | 2021-07-20 |
| 10838760 | Systems and methods for interrupt distribution | Jeffrey L. Freeman | 2020-11-17 |
| 10802932 | Data processing system having lockstep operation | Nancy Hing-Che Amedeo, Larry Alan Woodrum | 2020-10-13 |
| 10445133 | Data processing system having dynamic thread control | Jonathan J. Gamoneda, Jeffrey W. Scott | 2019-10-15 |
| 8975926 | Comparator and clock signal generation circuit | Wenzhong Zhang, Chris C. Dao, Yi Zhao | 2015-03-10 |
| 8717829 | System and method for soft error detection in memory devices | Ashish Sharma, James B. Eifert, Amit Gupta, Thomas W. Liston | 2014-05-06 |
| 8615610 | Interface system and method with backward compatibility | Gary L. Miller, Ray Marshall | 2013-12-24 |
| 8164378 | Device and technique for transistor well biasing | Stefano Pietri, Alfredo Olmos, Jefferson Daniel De Barros Soldera | 2012-04-24 |
| 7809980 | Error detector in a cache memory using configurable way redundancy | Florian Bogenberger, James B. Eifert | 2010-10-05 |